ASML has hit back against accusations about its latest EUV device

本文由半导体产业纵横(ID:ICVIEWS)编译自tomshardware

Recently, ASML hit back at criticism from analysts at SemiAnalysis, who argued that using the company's next-generation High-NA lithography equipment would not make much financial sense, at least for some chipmakers. In a recent interview with Bits and Chips, ASML's CFO said that High-NA is on track and healthy, and that the analytics firm underestimated its benefits. During the company's recent earnings call, ASML's CEO also answered questions about the report, saying that the new technology is "clearly the most cost-effective solution in terms of logic and memory chip manufacturing."

ASML's Twinscan EXE High-NA EUV lithography equipment is essential for producing next-generation process processes that are less than 2nm, but they are also much more expensive than existing Twinscan NXE Low-NA (low numerical aperture) extreme ultraviolet (EUV) lithography equipment, with some saying they cost between $300 million ~ $400 million. They also have other features, such as their large size, which is why some analysts believe that these tools are not suitable for all production lines.

As one might expect, ASML disagreed with this assessment, with the company's CFO telling Bits and Chips that the order was in line with the company's expectations, and that SemiAnalysis underestimated the value of reducing process complexity by avoiding costly double and quadruple exposures. He also said that one could simply talk to Intel about the complexities that come with double exposure, referring to Intel's failure at 10nm, at least in part due to the lack of EUV technology. Intel is a major customer of High-NA today and recently received the first batch of parts for the first High-NA device.

Simpler to manufacture

Double and quadruple exposure involves exposing the same layer of the wafer multiple times to create a smaller feature size than is usually possible, but it introduces defects that affect yield and is more costly than simply marking the layer in one step.

The overall cost of double and quadruple exposures with Low-NA devices, and compared to single exposures with High-NA devices, is a major point of contention between ASML and analysts.

By now, an avid reader might ask why High-NA's EUV is so cumbersome if Low-NA's EUV device can achieve the same feature size as the former by using dual and quadruple exposure devices?

ASML believes that the implementation of double exposure comes with certain drawbacks: EUV double exposure results in longer production times, a greater likelihood of defects, and can affect the performance of the chips produced. However, since the EXE:5000 has a resolution (CD) of 8nm, chipmakers can streamline their manufacturing processes.

Foundries certainly understand the pros and cons of using a high NA EUV scanner, so they have already started R&D work. "Our customers will start R&D in 2024-2025 and move into high-volume production in 2025-2026," ASML read in a statement.

ASML recently shared more details about its new High-NA devices, and here's a rundown of how these devices work.

New equipment is coming

ASML's next-generation Twinscan EXE has a 0.55 numerical aperture (NA) lens, so it will reach 8nm resolution, marking a substantial improvement for EUV devices that currently offer 13nm resolution. This means that it can engrave transistors that are 1.7 times smaller than a single exposure low numerical aperture device, resulting in a transistor density of 2.9 times.

Low numerical aperture lithography systems can achieve similar resolutions, but require an expensive double exposure process, albeit with two exposures. Achieving 8nm resolution is critical for chip production using sub-3nm process technology, which the industry plans to adopt between 2025~2026.

The use of high numerical aperture EUV allows fabs to avoid the need for EUV double exposure, streamline the process, potentially increase throughput, and reduce costs. But it also comes with a lot of challenges.

The latest Twinscan EXE lithography equipment is equipped with a 0.55 NA lens, which is completely different from existing machines. The main difference is the new and larger lenses. However, larger lenses require larger mirrors, which is why the Twinscan EXE device also has an anamorphic optical design.

This approach solves the problem of larger mirrors causing light to hit the reticle at a steeper angle, reducing reflectivity and hindering pattern transfer to the wafer.

Instead of uniformly shrinking the pattern, anamorphic optics magnify the pattern in different ways: 4x magnification in one direction and 8x magnification in the other. This reduces the angle of incidence of light on the reticle and solves the problem of reflectivity. In addition, this approach allows chipmakers to continue to use standard-sized reticles, minimizing the impact on the semiconductor industry. There is a problem with this method: it halves the size of the imaging field (from 33 mm x 26 mm to 16.5 mm x 26 mm), commonly known as High-NA, and halves the reticle size.

The halving of the imaging field size has prompted chipmakers to revise their chip design and production strategies. This change is especially important as high-end GPUs and AI accelerators increasingly challenge the limitations of imaging field size.

With anamorphic optics and exposure fields half the size of the Twinscan NXE system, the Twinscan EXE device needed to perform twice as many exposures per wafer, which would halve the productivity of existing machines. To maintain productivity, ASML has significantly increased the speed of the wafer and mask stages. The EXE has a wafer-level acceleration of 8g, which is twice that of the NXE, while its mask-level acceleration is 4x that of the NXE, at 32g.

This enhancement enables the Twinscan EXE:5000 to mark more than 185 wafers per hour at a dose of 20 mJ/cm², exceeding the Twinscan NXE:3600C's throughput of 170 wafers at the same dose.

ASML plans to increase production to 220 wafers per hour by 2025 using the Twinscan EXE:5200 to ensure the economic viability of High-NA technology in chip manufacturing. At the same time, the new node (i.e. lower resolution) requires a higher dose, so the Twinscan NXE:3600D increases the dose to 30 mJ/cm², despite the need for 160 wafers per hour. For some reason, ASML did not mention the performance of its EXE system at a dose of 30 mJ/cm².

Larger fabs

ASML's high NA EUV Twinscan EXE lithography equipment is physically larger than the low NA EUV Twinscan NXE lithography machine. ASML's Twinscan NXE, both existing and widely deployed, puts the light source underneath, which requires a very specific fab building configuration, which makes servicing these devices trickier. In contrast, the High-NA Twinscan EXE machine places the light source horizontally, simplifying fab construction and repair, but requiring more cleanroom space. On the other hand, this makes it trickier to upgrade existing fabs.

At the same time, TSMC already has several fabs built specifically for the Low-NA EUV Twinscan NXE lithography machine. Upgrading these fabs to High-NA Twinscan EXE equipment is a complex task.

Considering the cost of the equipment, the halving of the mask size, the complexity of installing these devices into existing fabs, the performance of existing Low-NA devices, and many other specific factors that cannot be considered in one framework, we can understand why analysts at China Renaissance believe that TSMC is not ready to adopt a high numerical aperture EUV device for the time being.

summary

High numerical aperture scanners have higher resolution, larger size, and half the exposure field, necessitating the development of new photoresists, metrology, thin film materials, masks, inspection tools, and possibly even the fabrication of new fabs. Essentially, the transition to High-NA equipment will require significant investment in new equipment and infrastructure, so adoption will not be easy.

However, High-NA EUV is the future, and the question of whether it is economically feasible to deploy it on a large scale will not be definitively answered until we see how many chipmakers put these devices into production and when.

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