Data centers utilize the channel between the transmitting and receiving systems to deliver valuable information accurately and efficiently. Poor channel performance can lead to signal integrity issues and affect the correct interpretation of the data being transmitted. Therefore, it is critical to ensure a high level of signal integrity when developing channel devices and interconnect products. Testing, identifying, and addressing the root causes of signal integrity issues in equipment can be a huge challenge for engineers. This article presents some simulation and measurement recommendations designed to help you design a device with excellent signal integrity.
The central processing unit (CPU) sends information to a light-emitting diode display, which is a typical example of a digital communication channel. This channel—all the media between the CPU and the display—includes interconnected devices such as graphics cards, cables, and onboard video processors. Each device, and their connections in the channel, interfere with the CPU's data transfer.
Signal integrity issues can include crosstalk, latency, ringing, and electromagnetic interference. Addressing signal integrity issues early allows engineers to develop high-performance products with greater reliability and also helps reduce costs.
Channel emulation
Engineers typically use electronic design automation software to create circuit simulations. Design automation software uses bitwise and statistical simulation techniques to provide fast and accurate channel simulations. The algorithm modeling interface is a standard used by design software to easily simulate multi-gigabit serial links from transmit to receive.
In addition to simulation software, engineers use signal analysis tools such as eye diagrams, mixed-mode S-parameters, and time-domain reflectance measurements. When simulating data transmission from transmitter to receiver, the eye diagram displayed on the oscilloscope can be used as an analysis parameter to help evaluate channel performance.
The width and height of the eye diagram are key indicators of signal distortion. A wide eye diagram means that the data is well transmitted. A closed eye diagram indicates a substantial reduction in signal integrity. If the eye diagram at the transmitter is open and the receiver is closed, the next step is to determine which devices or interconnects in the channel are causing the signal attenuation. Engineers can directly view the eye diagram of the transmitter's output, tracing it back to the receiver through each interconnect to identify the components that are causing the signal attenuation.
Figure 1: Example of a closed eye diagram and a normal eye diagram
Identify the root cause of signal attenuation
When describing the frequency characteristics of a given device, engineers can use the S-parameter as a criterion. The S-parameters of the interconnect, whether measured in the time domain or frequency domain, represent the characteristic model of the interconnect. This parameter covers all the characteristics of the signal from the time it enters one port to the time it leaves another.
In order to determine the root cause of signal attenuation, it is important to first determine what you can expect from the S-parameter. Comparing the expected value to the measured value can help identify areas of the channel that are causing signal integrity to decay.
Next, you need to dig deeper into the connection between the device under test and the device so that you can determine the root cause. For differential channels, the analysis can be performed using the mixed-mode S-parameters. The most common S-parameters are electromagnetic interference-related differential return loss (SDD11), differential insertion loss (SDD21), and differential-to-common-mode conversion (SCD21).
When analyzing transmission quality, it is also important to consider reflection factors. Whenever there is a transient impedance change, the signal is reflected. Reflections delay the returned original signal, as shown in Figure 2 below, and combine with the original signal to create interference.
Figure 2: Effect of reflection on signal quality
Explore and design signal integrity solutions
Once you've initially identified the root cause of signal attenuation, you'll need to research and determine the best solution. First, perform a simulation test after removing design flaws to verify that you have indeed found the root cause of signal integrity attenuation. Our suggestion is that instead of removing the problematic area as a solution, try adding equalization on the receiver, such as adding a decision feedback equalization
(DFE), continuous-time linear equalization in the frequency domain, or transmitter feedforward equalization in the time domain. Similarly, you can add equalization through simulation, and by observing the changes in the eye diagram in real time on the oscilloscope, you can test whether the equalization has solved the problem of signal integrity attenuation.
As shown in Figure 3, another test option is to apply the eye template before and after adding equalization. Before equalization is added, the images intersect, indicating that the eye diagram is closed. After equalization is added, the images no longer intersect, indicating that the eye diagram is open.
Figure 3: Comparison of eye diagram templates before and after using DFE
Signal integrity analysis
As your product design moves from simulation to hardware, you need a vector network analyzer (VNA) to test high-speed digital interconnects. First, you need to have an idea of what to expect from a channel, physical layer device, connector, cable, backplane, or printed circuit board. After the actual measurement results are obtained, the actual results are compared with this expected result. Our goal is to establish a reliable signal integrity workflow through software and hardware. Hardware measurement steps include instrument measurement setup, acquiring channel data, and analyzing channel performance.
For instruments with high dynamic range, such as vector network analyzers (VNAs), you need a thorough understanding of error correction to ensure the most accurate S-parameter measurements. Error correction includes calibration (error correction before measurement) and de-embedding (error correction after measurement). Check all node items in the channel except the DUT by adjusting the calibration and de-embedding reference points. The following describes the differences between calibration and de-embedding error correction and how to use them.
Signal calibration
By default, when the Vector Network Analyzer (VNA) is on, its reference plane is located on the front panel. When connecting a cable to the device under test, the calibration reference must use the short-open-load-straight-through method (SOLT), straight-through reflective line, or straight-through reflectance matching reference structure. SOLT is the most common method.
The cable can be connected directly to the DUT or clamp. The clamp is installed between the cable and the DUT, helping to be compatible with different types of connectors, such as HDMI, DisplayPort, Serial ATA, and PCI Express. In this example, the calibration reference plane includes the cable, while the de-embedded reference plane includes the fixture. When combining calibration error correction and deembedding, all interconnections to the DUT in the channel must be included. Once the DUT is connected, you can take measurements and perform post-measurement (de-embedding) error correction.
Figure 4: Test setup for calibration using a reference surface
De-embedding
Once the measurement is complete, set the de-embedding reference points on the input and output of the DUT so that the test fixture can be removed. By removing the test fixtures, the losses and reflections introduced into the system are removed, resulting in accurate S-parameter measurements and characterization of the DUT.
By comparing the S-parameter results of the two layers of correction (calibration and de-embedding) with the expected results, you can make model adjustments to match the actual measurements and then move on to device development.
Figure 5: Test setup for deembedding using reference planes
Overcome signal integrity issues
As data transmission speeds increase, signal integrity becomes increasingly important for channel devices and interconnect products. To ensure that your device has excellent signal integrity, you first determine the simulation results you want to achieve, and then compare them to actual measurements.
Next, a combination of signal analysis techniques, such as the eye diagram displayed on the oscilloscope, and simulation software can be used to find the root cause of signal attenuation. The next step is to identify the right solution, using software and hardware to establish a reliable signal integrity workflow.
A high-quality vector network analyzer (VNA) must be used, calibration reference planes must be set up to perform S-parameter measurements, and de-embedding reference planes must be set up to properly remove fixtures. The measurement results will include accurate S-parameters and reliable DUT characteristics. By addressing signal integrity issues early, you can optimize your circuit design for superior device performance and competitive pricing.