In the 2nm campaign, TSMC began to defend

Today, the competition for chip manufacturing technology is becoming more and more intense. The two giants, TSMC and Intel, are competing to launch more advanced process technologies in the field of 2nm to 1nm processes, in an effort to seize market opportunities.

In this showdown of advanced processes, do you trust TSMC more? or are you more optimistic about Intel?

In terms of technology, TSMC is known for its advanced process technology. From 7nm to 3nm, TSMC has always maintained a leading position and constantly refreshed the limits of semiconductor processes. Although Intel was once ahead in process technology, it suffered many delays in the 10nm process node, and the process has been relatively backward for many years.

In this context, many people believe that facing TSMC is Intel's radical move. So why does Intel dare to face TSMC, and what are the driving forces behind these two major manufacturers?

Before understanding these factors, it is necessary to understand the history of TSMC's competition with Intel over the years.

01

TSMC's history of competition with Intel

In the PC era, Intel is undoubtedly the industry hegemon, sitting on the CPU market for PCs and servers. Intel's business model is to tie chip design and manufacturing together, with the design department constantly iterating to design newer and faster CPUs, and the manufacturing department investing huge sums of money to produce generations of new products.

In the past two decades, Intel processors have closely followed the "Moore's Law", from 45nm, to 32nm, and then to 22nm.

Until the 14nm process node, Intel was ahead of the curve.

TSMC is different from Intel's IDM model, and its business positioning is clear from the beginning: only do downstream manufacturing, and do not compete with customers in chip design. In the more than 20 years since TSMC was founded, it once existed as Intel's "little brother".

With continuous innovation and technology accumulation, TSMC has attracted the attention of Apple. Since 2014, Apple, which has developed its own chips, began to hand over chip foundry orders to TSMC, and after harvesting Apple, a major customer, TSMC not only gained the opportunity for rapid technological progress, but also harvested business growth in the next ten years. Since then, orders from TSMC have poured in, and almost all chip design giants such as Qualcomm, NVIDIA, and AMD have begun to cooperate with TSMC. TSMC has also gradually gained the strength to compete with Intel.

Up to 10nm, Intel was limited by yield issues, its 10nm node did not choose EUV, chose to continue to use ArF DUV, and did not increase the transistor density by 2x according to Moore's Law, but risked increasing it by 2.7x, and at 10nm Intel introduced the expensive material cobalt instead of copper, and the hardness of cobalt also brought various problems.

At this stage, Intel's biennial upgrade rule was pressed the pause button, and TSMC began to overtake Intel. Since then, from 7nm to 3nm, the contestants have changed from three to TSMC and Samsung, and even under the "temptation" of TSMC's advanced manufacturing process, Intel began to outsource chip manufacturing to TSMC.

In the subsequent competition between TSMC and Samsung, TSMC won more advanced process orders with yield advantages. Samsung has also made improving yield a top priority and is vigorously developing 3nm. Just when TSMC and Samsung are in the midst of a fierce battle around the 3nm advanced process, the long-dormant giant Intel is quietly involved in this battle and challenges TSMC in the next generation of process technology.

Many people believe that Intel's move is too aggressive, after all, it has lagged behind in the field of advanced processes for many years. However, Intel CEO Pat Gelsinger said that Intel will beat TSMC in the next few years.

02

Two drivers of Intel's counterattack

I believe that there are two reasons for Kissinger's decision, one is that Pat Gelsinger has an in-depth analysis and a clearer understanding of the current gap between the two companies, which allows him to better assess the strengths and weaknesses of Intel and TSMC.

The outside world declares that TSMC's current process has developed to 3nm, compared to Intel's current 4 (5nm) process stage. In fact, few people know that the naming of today's process is a "game" in itself.

Prior to 1990, the reduction in gate length was almost entirely linear, with each generation of transistors being 0.7 times longer and wider than the previous generation (length 0.7 * width 0.7 = 0.49), that is, the area of a single transistor was reduced to 0.5 times the original size, confirming Moore's Law description of doubling the density of transistors. For example, 180nm> 130nm> 90nm> 65nm> 45nm> 32nm>22nm, where "X" refers to the length of the chip gate, that is, the distance from the source to the drain of the MOS transistor. As the number of advanced processes is smaller, the higher the density of the corresponding transistors, the lower the power consumption of the chip, and the higher the performance.

In the subsequent evolution of the technology, the process node reduction speed is accelerated, about 0.72 times, and it is no longer fully linear. Field-effect transistors are also gradually detached from the original fixed structure, such as the spatial structure transistor of FinFET, the channel becomes three-dimensional surrounding, and the channel length gradually does not represent the highest accuracy of the process. 7nm, 5nm, and 3nm are no longer representative of channel length, it is just a number as an equivalent length.

Since then, the process naming rules of the two major chip manufacturers, TSMC and Samsung, have also quietly changed.

Intel's gate spacing in the 10nm process is at the level that TSMC and Samsung can only achieve at 7nm, and even in the comparison of logic transistor density, Intel has a considerable advantage. At 10nm, Intel's logic transistor density is about 101 million units/mm2, while TSMC only has 48 million units/mm2.

It is worth noting that there are some differences in the way each indicator is calculated.

As Philip Wong, TSMC's vice president of research, said at Hot Chips 31: Now "Xnm" represents only an iteration of technology, just like a car model that has no clear meaning. This is also the reason why Intel's "new chip process naming rules" later, using Intel 7, Intel 4, Intel 3, Intel 20A, Intel 18A and other rules to redefine the chip manufacturing process. The technological advancement of chips cannot be judged only by how many nanometers the process is.

There is no doubt that TSMC's pace in advanced manufacturing processes is indeed faster and more stable, and the rich orders accumulated by TSMC over the years have undoubtedly provided it with huge power and resources, and constantly promoted it to make greater breakthroughs in technology research and development and yield improvement. Therefore, it is not easy to challenge TSMC.

Second, whether it is technological innovation or capacity reserves, Intel has been brewing for a long time, and Intel is waiting for the opportunity to start this counterattack. Let's take a look, what "big moves" has Intel prepared to face TSMC?

03

In order to meet TSMC, what preparations has Intel made?

Spin-off of the foundry business

In June 2023, Intel issued a press release announcing the restructuring of its manufacturing business, including the existing self-used IDM manufacturing and foundry (IFS) business, which will operate independently and generate profits in the future. In this new "in-house foundry" model, Intel's product business unit will work with the company's manufacturing business group in a similar way to Fabless and external foundries.

Intel's spin-off foundry business also has two advantages. One is to reduce costs and increase efficiency. After Pat Kissinger's planned spin-off, it could save $3 billion in costs and contribute 6% of profits in 2023. In 2023, the industry will earn more than $20 billion, replacing Samsung as the world's second-largest foundry. Reduce costs by $30 billion in the next three years, and save $8 billion ~ $10 billion by 2025. And after the spin-off of the foundry business, Intel can choose foundries such as TSMC for chip manufacturing like AMD, and use the latest manufacturing technology of foundries to improve chip performance and reduce costs. This will allow Intel to be more competitive in the market and better able to respond to the challenges of competitors such as AMD.

Second, the spin-off of the foundry business can avoid competition with customers, because Intel found in the survey that all potential foundry business customers said that if they need to compete with Intel for foundry resources, then they will not choose Intel's foundry services. Not only that, in order to dispel the concerns of foundry customers, Intel will set up a firewall to distinguish customer information and protect customers' sensitive design data. In this way, Intel is expected to obtain advanced process orders from Apple, Nvidia and other chip manufacturers in the future.

Backside power supply technology and RibbonFET are introduced

In a December 2023 interview, Kissinger highlighted the 18A process (1.8nm) versus TSMC's N2 (2nm) node. Both 18A and N2 will utilize GAA transistors (RibbonFETs), and 18A will feature BSPND (Backside Power Delivery Network), a backside power delivery technology that optimizes power and clocking.

Back-side power technology is a promising innovation, and Intel became the first company to put it into practice, providing advantages for thermal management and overall performance by delivering power to the back of the chip instead of the front. Efficient heat dissipation and power transfer help optimize chip layout and design, improving functionality and heat distribution.

PowerVia is a completely revolutionary technology. For most readers, the best analogy is EUV. As early as 2019, TSMC began to use EUV lithography machines in chip mass production, knowing that EUV brings new challenges, especially a series of new problems that are difficult to solve, such as EUV mask contamination and some resists. Intel will only use EUV when it mass-produces Intel4 in 2023.

BSPDN also requires process improvements of a similar magnitude. It is reported that TSMC's insertion of the BSPDN could happen by 2026 at the latest. In the coming years, BSPDN has the potential to have multiple design advantages, and Intel is likely to lead the PowerVia as well.

Gelsinger noted that Intel offers better area efficiency in terms of backside power technology. This means lower costs, better power delivery, and higher performance. He believes that the Intel 18A is slightly ahead of the N2 because of its more powerful transistors and greater power transfer capabilities. In addition, Intel can offer a more competitive price advantage compared to TSMC.

拿下首套 High-NA EUV

Recently, Intel announced that it has received the first ASML extreme ultraviolet lithography machine with 0.55 numerical aperture (High-NA) on the market, which is expected to be used in the next two to three years after the process node of Intel's 18A process technology.

In contrast, TSMC has taken a more cautious approach, and the industry expects that TSMC may not adopt High-NA EUV lithography until the A1.4 process, or after 2030.

According to previous reports, ASML will produce up to 10 new generation high-NA EUV lithography machines in 2024, of which Intel has booked as many as 6 units. The industry pointed out that at least initially, the cost of High-NA EUV may be higher than that of Low-NA EUV, which is also the reason for TSMC to wait and see for the time being, and TSMC prefers to adopt mature technologies with lower costs to ensure product competitiveness. High-NA EUVs require higher light source power to drive finer exposure sizes, which accelerates the wear and tear of projection optics and reticles, negating the benefits of higher throughput.

But what is certain is that Intel will be ahead of its competitors when it comes to high NA learning, which will give it several advantages. Specifically, since Intel is likely to be the first company to launch high-volume production with a high numerical aperture tool, it is inevitable that the fab tooling ecosystem will follow its requirements. The above requirements may translate into industry standards, which could give Intel an edge over TSMC and Samsung.

Expansion of advanced packaging

While Intel is actively investing in the research and development of advanced processes, it is simultaneously firing in the field of advanced packaging.

In 2023, Intel expanded its advanced packaging capacity in Malaysia, with the goal of quadrupling its advanced packaging capacity by 2025 compared to the current level. It is expected that after Intel combines advanced processes and advanced packaging capabilities, its "one-stop production" strength will increase greatly and it will be more competitive in the field of wafer foundry.

TSMC and Samsung are actively deploying advanced packaging technologies. In terms of TSMC, it focuses on "3D Fabric" advanced packaging, including InFo, CoWoS and SoIC solutions, and Samsung also develops I-cube, X-Cube and other packaging technologies. Intel's advanced packaging technologies include 2.5D EMIB and 3D Foveros solutions.

Intel did not disclose its total 3D Foveros packaging capacity at this stage, only emphasizing that in addition to Oregon and New Mexico in the United States, there will also be relevant production capacity in the new Penang factory in the future, and the combined 3D packaging capacity of these three bases will quadruple by 2025. Robin Martin, vice president of Intel, said that the new Penang factory will become Intel's largest 3D Foveros advanced packaging base in the future.

With the evolution of advanced manufacturing processes, the development trend of chiplet and heterogeneous integration is clear, and the outside world believes that Intel's 2.5D/3D advanced packaging layout will not only strengthen its own processor and other product strength, but also a major selling point for it to strive for more wafer foundry service business in the future.

Mass production is even earlier

According to Intel's new statement, chips made using Intel's 18A process will appear in the first quarter of 2024, and the first mass production products will be available in the second half of 2024. In contrast, TSMC's N2 process will not be mass-produced until the second half of 2025, and Intel is theoretically a year ahead in time.

In the face of Intel's series of heavy attacks, what does TSMC think?

04

TSMC has a number of first-mover advantages

In the face of Intel's challenge, TSMC did not show weakness.

TSMC President Wei Zhejia said that according to internal evaluations, the N3P process is comparable to Intel 18A technology in terms of performance and energy efficiency, but it is earlier in market, more mature in technology, and much lower in cost. It also reaffirmed that TSMC's N2 process is superior to competitor Intel 18A, which will be the most advanced technology in the semiconductor industry when launched in 2025.

TSMC plans to adopt GAAFET transistors at the 2nm process node, and will introduce Nanosheet GAA transistors and add backside power rail technology to the N2P process to be released in 2026, while the manufacturing process still relies on existing EUV lithography technology. TSMC believes that after the introduction of a new generation of technology, the N2 process will win in terms of power, performance, and area.

The accumulation of a number of technical advantages

In the 3nm process race with Samsung, TSMC is not in a hurry to use GAAFET. With its technological advantages and accumulation in process leadership and production yield, it is fully capable of competing with Samsung's MBCFET (Samsung's multi-bridge crystal FET technology, which can be classified as GAA technology) architecture.

TSMC's success stems from the accumulation of a number of technological advantages. First of all, its long-term investment has obtained leading technology research and development advantages. For example, in order to match the yield of the new process technology, TSMC has successfully produced a 32 Mb nano-sheet SRAM on the nano-sheet structure, which has obvious advantages in low voltage power consumption, in 2D materials, TSMC has obtained very high performance on-current based on 2D sulfide materials including molybdenum sulfide and tungsten sulfide, and in power management, TSMC researchers have embedded carbon nanotubes into a CMOS design to replace them The power gating of the current provides new ideas for further scaling in the future.

The second is the optimization and transformation of the process. In order to cope with the crisis of Moore's Law approaching failure, only from the perspective of scaling transistors, increasing density to improve chip performance is failing. TSMC has promoted a number of front-end and back-end 3D packaging technologies to improve chip performance. For example, SOIC 3D stacking technology is implemented in the front end of chip manufacturing, and CoWoS and InFo 3D packaging technology are implemented in the back end. These technologies help to achieve transistor scaling while further improving yields.

First use of GAA

The GAAFET technology used by TSMC for the first time in the 2nm process is different from the FinFET architecture used in the 3nm and 5nm processes, and the GAAFET architecture is based on the Surround Gate (GAA) process, which can solve the physical limitations of FinFETch due to process scaling, such as current control leakage.

TSMC is widely regarded as a conservative but robust developer of process technology, preferring to ensure the maturity and reliability of new technologies before deploying them, rather than rushing to bring new technologies to market. This approach reduces the risk of technical failure, increases the yield and quality of its chips, and thus ensures customer satisfaction. For example, Samsung started using EUV in its 7nm process in 2018, yet TSMC chose to wait. EUV was not started in the N7+ process in 2019 until the stability and maturity of the EUV tool was confirmed, and the associated issues were resolved or at least determined.

This cautious approach helps TSMC ensure the stability and predictability of its process technology to deliver high-quality chips to its customers.

TSMC's use of GAA this time must be fully prepared and planned, and the 2nm generation may be expected to see a new round of TSMC outbreak.

TSMC N2 is an extension of N3

TSMC's 2nm technology is a continuation of 3nm technology. For a long time, TSMC has firmly followed the evolution strategy of one process node at a time, making steady progress and making breakthroughs. Now, in the journey towards 2nm manufacturing, we can foresee that it will inherit many advantages of 3nm technology, like an excellent relay in the relay race, passing on the excellent results of the previous baton to the next baton. Therefore, in this advanced process war, TSMC has a first-mover advantage in terms of technology maturity and yield control.

Customer trust

TSMC's success depends not only on advanced chip manufacturing technology, but also on its foundry-only business model, good yield, and customer trust. In the 3nm generation, TSMC's offer is more than $20,000, which is $4,000 higher than the 4nm/5nm foundry price. This high price is intimidating to many customers, but Apple still chooses TSMC foundry and takes up all the production capacity. Although Samsung strives to surpass TSMC in the field of wafer foundry, TSMC still maintains an absolute leading position, taking most of the 3nm orders in the market. Now, in addition to Apple, customers such as Nvidia, AMD, Qualcomm and MediaTek are planning to purchase second-generation 3nm process (N3E) capacity.

However, it should be noted that chip manufacturers do not want to dominate the chip manufacturing link in order to have more say in order to have more say, once the yield rate of Intel's advanced process chips and other data are better than or only equal to TSMC, then Apple, Qualcomm, Nvidia and many other American companies are likely to choose Intel. After all, Nvidia executives have made it clear that they are willing to consider letting Intel make chips.

Finally, the process technology battle between Intel and TSMC will undoubtedly become the focus of attention in the semiconductor industry in the coming years. Judging from the timeline disclosed so far, the R&D answer for the 2nm process will be revealed in 2025. We'll see how technology evolves in the future. We also look forward to seeing more innovation and technological breakthroughs in 2025 and beyond.