PLCs in Automated Manufacturing Systems (Part 9)

9 Latches, timers, counters, etc

9.1 Introduction

More complex systems can't be controlled by combinatorial logic alone. The main reason is that we can't or choose not to add sensors to detect all conditions. In these cases, we can use events to estimate the state of the system. Events commonly used by PLCs include:

PLC First Scan - Indicates that the PLC has just started

The time since the input on/off - Delay

Event Count - Wait for a certain number of events to occur

Latch or Unlock - Locks or closes something

The common theme of all of these events is that they are all based on one of two questions: "How much?" or "How much?" An example of an event device is shown in Figure 9.1. The input for the device is a button. When the button is pressed, the input of the device becomes on. If the button is then released and the device turns off, it is a logical device. If the device remains on when the button is released, it will be an event-based device. In summary, a device is event-based if it responds to one or more things that happen. If the device has only one way to respond to instant input, it's logical.

9.2 Latches

The latch is like a sticky switch - it opens when pressed, and stays in that position, and must be pulled to release and close it. In ladder logic, the latch uses one instruction to latch and the second to unlock, as shown in Figure 9.2. An output marked with an "L" will turn on output D when input A becomes true. Even if A becomes false, D will remain open. If input B becomes true, and the output marked with a "U" becomes true (note: this can be a bit counterintuitive at first), output D will be turned off. If an output is latched as on, it retains its value even if the power is turned off.

The operation of the ladder logic in Figure 9.2 is illustrated by the sequence diagram in Figure 9.3. A timing diagram shows the values of inputs and outputs over time. For example, the value of input A is low (false) at first, then goes high (true), lasts for a short period of time, and then goes low again. Here, when input A becomes true, both outputs turn on. There is a slight delay between the input change and the output change due to the program scan time. Here, the dotted lines represent the output scan, sanity check, and input scan (assuming they are very short). The space between the dotted lines is the time when the ladder logic scans. Consider that when A initially becomes true, it will not be detected until the first dashed line. Then, there is a delay to the next dashed line during the ladder logic scan, followed by the output at the next dashed line. When A eventually becomes false, the regular output C is turned off, but the latched output D remains open. Input B will unlock Output D. Input B is initiated twice, but the first start is not long enough to be detected by the input scan, so it is ignored. On the second boot, it unlocks output D and outputs D off.

Figure 9.3 A Timing Diagram for the Ladder Logic in Figure 9.2

The timing diagram in Figure 9.3 is more detailed than the usual sequence diagram in the timing diagram in Figure 9.4. Short pulses are often undesirable and can be designed to keep them out of the system by extending the duration of the pulses or decreasing the scan time. The ideal system runs very fast and doesn't have aliasing.

Figure 9.5 shows a more complex latch example. In this example, the address is for the Allen-Bradley MicroLogix controller. Input starts with I/, followed by the input number. The output starts with O/ followed by the output number.

In ladder logic, the normal output should only appear once, but latch and unlock instructions can occur multiple times. In Figure 9.5, the normal output O/2 is repeated twice. When the program runs, it will check the fourth line and change the value of O/2 in memory (keep in mind that the output sweep does not happen until the keystone sweep is complete). Then explain the last line, which overrides the value of O/2. Basically, only the last line will change O/2.

Not all PLC suppliers use latches universally, others such as Siemens use flip-flops. They behave like latches, but with different symbols, as shown in Figure 9.6. The trigger here is an output block connected to two different logical trapezoids. The first trapezoid shown has an input A connected to the S setting terminal. When A is true, the output value Q will become true. The second trapezoid has an input B connected to the R reset terminal. When B is true, the output value Q will be turned off. The output Q will always be the opposite of Q. Note that the values of S and R are equivalent to the values of L and U in the previous example.

9.3 Timers

There are four basic types of timers, as shown in Figure 9.7. The power-on delay timer will wait some time after the keystone logic coil is true before turning it on, but will turn off immediately. The de-energized delay timer will turn on as soon as the keystone logic coil is true, but there will be a delay before it is turned off. Consider an example of an old car. If you turn the ignition and the vehicle doesn't start immediately, that's a power-on delay. If you turn the ignition to stop the engine, but the engine doesn't stop until a few seconds later, that's the de-energizing delay. A power-on delay timer can be used to bring the oven to temperature before starting production. The de-energized delay timer allows the cooling fan to continue running for a preset amount of time after the oven is turned off.

The hold-time timer adds up the timer's on or off time, even if the timer never completes. The non-holding timer will calculate the delay time from zero each time. Typical applications for hold-up timers include tracking the time required for maintenance. A non-holding timer can be used to start the button to set a short delay before the conveyor begins to move.

Figure 9.8 shows an example of an Allen-Bradley TON timer. The ladder logic coil has a single input A and a TON function block (note: this timer block may look different for different PLCs, but it will contain the same information). The information inside the timer block describes the parameters of the timer. The first item is the timer number T4:0. This is where the timer information is stored in the PLC memory. T4: Indicates that it is timer memory, and 0 indicates that it is in the first position. The time base is 1.0, which means that the timer will work at 1.0-second intervals. Other time bases are available in fractions and multiples of seconds. The default value is the delay time of the timer, which in this case is 4. To find the delay time, multiply the time base by the preset value of 4 * 1.0 seconds = 4.0 seconds. The accumulator value gives the current value of the timer and is 0. As the timer runs, the accumulator value will increase until the preset value is reached. As long as input A is true, the EN output will be true. The DN output will remain false until the accumulator reaches a preset value. The EN and DN outputs cannot be changed while programming, but are very important when debugging ladder logic programs. The second line of the ladder logic uses the timer DN output to control another output B.

The timing diagram in Figure 9.8 illustrates the operation of the TON timer with a 4-second pass delay. A is the input of the timer, and whenever the timer input is true, the EN enable bit of the timer will also be true. If the accumulator value is equal to the preset value, the DN bit is set. Otherwise, the TT bit will be set and the accumulator value will start to increase. The first time A is true, it is only true for 3 seconds, then it turns off, after which the value is reset to zero (note: in a hold timer, this value will remain at 3 seconds). The second time A is true, it lasts for more than 4 seconds. After 4 seconds, the TT bit is off and the DN bit is on. However, when A is released, the accumulator resets to zero, and the DN bit is turned off.

You can enter a value for the accumulator at programming time. When the program downloads, the value will be in the first scan of the timer. If the TON timer is not enabled, the value will be set to zero. Typically, zero is entered for the preset value.

The timer in Figure 9.9 is the same as the timer in Figure 9.8, except that it is of the hold type. The most important difference is that the accumulator value does not reset to zero when input A is turned off. As a result, the timer will turn on earlier and will not turn off after it is turned on. A reset instruction will be displayed later, allowing the accumulator to be reset to zero.

Figure 9.10 shows a shutdown delay timer. The timer has a time base of 0.01 seconds, a default value of 350, and a total delay of 3.5 seconds. As before, the timer's EN enablement matches the input. When A is true, the DN bit is on. When input A is off and the accumulator is counting, the DN bit is also on. The DN bit is turned off only when input A is turned off long enough for the accumulator value to reach the preset value. This type of timer is not holdable, so the accumulator resets when input A becomes true.

Hold-on shutdown delay (RTF) timers are less widely used and are therefore not included in many PLC vendors.

A sample program is shown in Figure 9.11. There are a total of four timers used in this example, which are T4:1 to T4:4. Timer instructions use a shorthand symbolic notation in which a time datum and a preset value are combined as a delay. All four different types of counters have input I/1. When the TON counter T4:1 is complete, the output O/1 will turn on. All four timers can be reset using input I/2.

The timing diagram of this example is shown in Figure 9.12. When input I/1 is turned on, the TON and RTO timers start counting and turn on after 4 seconds. When I/2 becomes true, they are reset and start counting for another second before I/1 is turned off. After the input is turned off, both TOF and RTF start counting, but neither reaches the 4-second preset. Input I/1 is turned on again and both TON and RTO start counting. The RTO opens one second earlier because it stores 7 seconds in a time period of 8-1 seconds. After I/1 is turned off again, all shutdown delay counters start counting down to a 4-second delay and turn on. These patterns occur consistently throughout the chart.

Consider the short trapezoidal logic program used in Figure 9.13 to control the heating of the oven. The system is activated by pressing the start button, which turns on the automatic mode. If you press the stop button, you can stop the system from running (remember: the stop button is usually closed). When the automatic mode starts, the TON timer is used to sound an alarm for the first 10 seconds that the oven is about to start, after which the alarm stops and the heating coil starts working. When the oven is turned off, the fan will continue to blow for 300 seconds or 5 minutes.

Figure 9.14 shows a program that flashes lights once per second. When the PLC starts, the second timer will be turned off, the T4:1/DN bit will be turned off, so the normally closed input of the first timer will be turned on. T4:0 will start counting until it reaches 0.5 seconds, and when it is done, a second timer will start counting until it reaches 0.5 seconds. At that point, T4:1/DN will become true and the input to the first timer will become false. Then T4:0 is set back to zero, and then T4:1 is set back to zero. The whole process starts from scratch again. In this example, the first timer is used to drive the second timer. This arrangement is often referred to as cascade and can use more than two timers.

9.4 Counters

There are two basic types of counters: increment counters and decrement counters. When the input to the increment counter is true, the accumulator value is increased by 1 (regardless of how long the input is true). If the accumulator value reaches the preset value, the DN bit of the counter will be set. The decrement counter will reduce the accumulator value until the preset value is reached.

Figure 9.15 shows an Allen Bradley Increment Counter (CTU) instruction. This instruction requires memory in the PLC to store values and status, in this case C5:0. C5: Indicates that it is counter memory, and 0 indicates that it is the first location. The default value is 4 and the value in the accumulator is 2. If input A changes from false to true, the value in the accumulator will increase to 3. If A becomes false again and then true again, the accumulator value will increase to 4 and the DN bit will turn on. The count can continue to exceed the preset value. If input B is true, the value in the counter accumulator will become zero.

Decrement counters are very similar to increment counters, in fact they can be used simultaneously on the same counter memory location. Consider the example in Figure 9.16 where the example input I/1 drives an incrementing instruction for the counter C5:1. Enter I/2 to drive decrement instructions for the same counter position. The preset value of the counter is stored in memory location C5:1, so the increment and decrement instructions must have the same preset value. Input I/3 will reset the counter.

The timing diagram in Figure 9.16 illustrates the operation of the counter. If we assume that the value in the accumulator starts at 0, then the I/1 input increments it to 3, and then it turns on the counter C5:1. It is then reset by input I/3 and the accumulator value becomes zero. The input I/1 then pulses again, causing the accumulator value to increase again until a maximum of 5 is reached. Entering I/2 then causes the accumulator value to decrease below 3 and the counter turns off again. Input I/1 then causes it to increment, but Input I/3 resets the accumulator to zero and the pulse continues until 3 near the end.

The procedure in Figure 9.17 is used to remove 5 out of every 10 parts from a conveyor belt with a cylinder. When a part is detected, both counters will increment by 1. When the sixth part arrives, the first counter will be completed, allowing the cylinder to move on any part after the fifth. The second counter will continue until the 11th part is detected, and then both counters will be reset.

9.5 主控继电器（MCRs）

In electrical control systems, the master control relay (MCR) is used to shut down a part of the electrical system, as previously shown in the Electrical Wiring chapter. This concept is also implemented in trapezoidal logic. Part of the trapezoidal logic can be placed between two lines containing the MCR. When the first MCR coil is active, all intermediate trapezoidal logic will be executed up to the line where the second MCR coil is located. When the first MCR coil is inactive, the keystone logic will still be checked, but all outputs will be forced off.

Consider the example in Figure 9.18. If A is true, the subsequent ladder logic will be executed, just like normal. If A is false, the subsequent ladder logic will be checked, but all outputs will be forced off. The second MCR function appears in a row, marking the end of the MCR block. After the second MCR, the program execution returned to normal. When A is true, X will be equal to B, and Y can be turned on by C and closed by D. However, if A becomes false, X will be forced to close and Y will remain in its last state. Using MCR blocks to remove parts of a program will not significantly increase the speed of program execution, as the logic will still be checked.

If the MCR block contains another function, such as a TON timer, turning off the MCR block will force the timer to close. The general rule is that normal outputs should be placed outside the MCR block, unless they must be forced to shut down when the MCR block is closed.

9.6 Internal Relays

In a simple program, the input is used to set the output. More complex programs also use internal memory locations that are not inputs or outputs. These are sometimes referred to as 'internal relays' or 'control relays'. Skilled programmers often refer to this as 'bit memory'. In Allen Bradley PLC, these addresses start with 'B3' by default. The first bit in memory is 'B3:0/0', where the first zero represents the first 16-bit word and the second zero represents the first bit in the word. The bit sequence is shown in Figure 9.19. Programmers are free to use these memory locations as needed.

An example of the usage of bit memory is shown in Figure 9.20. The first trapezoidal logic bar will open the internal memory bit 'B3:0/0' when input 'hand_A' is activated and input 'clear' is not. (Note that B3 memory is used as both input and output.) The second line of trapezoidal logic is similar. In this case, when both inputs are activated, the output 'press on' is active.

Bitmemory is briefly covered here, as it is important for design techniques in later chapters, but will be covered in more depth after that.

9.7 Design Cases

To highlight the principles presented in this section, design examples are provided below. It is recommended to try to develop ladder logic before looking at the solutions provided.

9.7.1 Basic Counters and Timers

Problem: Develop ladder logic so that it lights up the output light 15 seconds after switch A is turned on.

Problem: Develop ladder logic so that switch A turns on a light after 10 times of closure. Pressing button B will reset the counter.

9.7.2 More Timers and Counters

Problem: Develop a program so that output B is latched within 20 seconds of input A being turned on. Once A is pressed, a delay of 10 seconds must elapse before A can produce any effect again. After A is pressed 3 times, B will be turned off.

9.7.3 Deadlock Switches

Problem: One motor will be controlled by two switches. The start switch will start the motor, and the stop switch will stop the motor. If you use a stop switch to stop the motor, you must throw the start switch twice to restart the motor. When the motor is active, a light should be lit. The stop switch will be connected as a normally closed switch.

9.7.4 Conveyors

Problem: Running the conveyor by switching the motor on and off. We are using an optical detector to locate parts on a conveyor. When the optical sensor triggers, we want to wait 1.5 seconds and then stop the conveyor. After a delay of 2 seconds, the conveyor will restart. We need to use the start and stop buttons - a light should be lit when the system is active.

9.7.5 Accept/Reject Classification

Question: For the conveyor in the previous case, we will add a classification system. A measuring instrument that indicates the quality of the part is connected. If the part is good, it will move on. If the part is broken, we don't want a delay of 2 seconds, but start a cylinder.

9.7.6 Shearing presses

Question: The basic requirements are as follows,

1. The toggle start switch (TS1) and the limit switch on the safety gate (LS1) must be activated at the same time to activate the solenoid valve (SOL1) to extend the cylinder to the top of the part.
2. During the activation of the stamping solenoid, it must remain active until the limit switch (LS2) is activated. A second limit switch indicates the end of the stroke. At this point, the solenoid valve should be deenergized, thus retracting the cylinder.
3. When the cylinder is fully retracted, the limit switch (LS3) is activated. The cycle must not be restarted until this limit switch is activated.
4. A cycle counter should also be included to allow counting of produced parts. When the value exceeds 5000, the machine should turn off and light up an indicator light.
5. A security check should also be included. If the cylinder solenoid is active for more than 5 seconds, this indicates that the cylinder may be stuck or the machine is faulty. If this is the case, the machine should be turned off and the maintenance indicator should be lit.

9.8 Summary

• The Latch and Unlatch commands will keep the output on, even when the power is off.

• The timer can be turned on or off with a delay. A hold-up timer retains a numeric value, even when it is inactive. The hold-up timer needs to be reset.

• The counter can be counted forward or backward.

• When the timer and counter reach the preset limit, the DN (Done) bit is set.

• MCRs (Master Control Relays) can force off a portion of the ladder logic.