Students often have questions about the memory when developing, and the following will use the Huaqing development board (FS4412) of the Exynos4412 chip as an example.
The manuals used are as follows:
FS4412_CoreBoard_V2.pdf
FS4412-DevBoard-V5.pdf
SEC_Exynos4412_Users Manual_Ver.1.00.00.pdf
Briefly
The exynos4412 storage is divided into the following blocks:
iROM: Starts the mirror area, which stores the programs preset by Samsung, also called bl0
iRAM: internal memory area, loading the startup program selected by OM, usually loading bl1, bl2
SMC: Static Memory Area, Static Read Only Memory Controller, usually used to map devices on the external bus, such as network cards, etc., this area is divided into 4 banks, each 16M (corresponding to the hardware manual xm0 at the beginning)
SFR: Special function register area, usually used to map SOC internal devices such as GPIOs
DMC: Dynamic memory area, which is our usual sense of memory.
PS: Dynamic memory (because the dynamic memory itself does not supply power, it needs to be constantly powered to refresh and save data, so it is called dynamic memory) (corresponding to the hardware manual xm1 and xm2 at the beginning)
Principles of Hardware (SMC)
There is 1 separate SMC in the Exynos 4412, divided into 4 banks
There are no row addresses and column addresses, and the available memory size of the entire chip: 2^8bit=256/16=16Byte
When selecting external devices, only 0 or 1 can be selected.
Hardware Principles (DMC)
The Exynos 4412 has two independent DRAM controllers, called DMC0 and DMC1, which can connect two different sets of DDR memory. DMC0 and DMC1 each support 1.5GB of DRAM, both support DDR2/DDR3 and LPDDR2, 512 Mb, 1 Gb, 2 Gb, 4 Gb and 8 Gbit memory devices, support 16/32 bit bit width. The address corresponding to DRAM0 is 0x4000_0000~0xAFFF_FFF a total of 1.5GB, and the address corresponding to DRAM1 is 0xA000_000~0x0000_0000 a total of 1.5GB.
The 1GB DRAM of the 4412 is a combination of 4 DDR3 chips with a size of 256M*16 (you can get it by looking at the chip model)
Chip model: K4B4G1646B-HYXX
First bit: K represents memory
The second bit: 4 indicates the falsh type DRAM
Third place: B stands for DDR3
4th~5th place. Density (note: the actual unit should be bits, not Byte), ours is 4Gbit = 4G/16 (data bits) = 256MByte
6th~7th place. organization: The number of data line pins, ours is 16
After the analysis is completed, there are 4 such memory chips on the development board, and the total capacity is 256M*4=1G
The four DDR chips are divided into groups of two to form 32-bit data, and all four are attached to DMC0
The general diagram is as follows:
The exploded chart is as follows (only half listed):
As can be seen from the above two figures, the four DDR chips are divided into two groups of two, forming 32-bit data, and the four are attached to DMC0, as follows:
· A 16-bit piece on the left and 16 bits on the right make up 32 bits of data
· All chip selections are attached to CS0:
· Number of bank lines:
3 routes (BA0-BA2), there are 2^3 combinations, that is, on one chip, there are 8 banks
· Address line
Number of address lines: 15 (A0-A14)
ps: A chip memory supports: 2^(number of bank lines + address lines) = 2^33 = 8Gbit/16=512MByte
· Row and column address lines
nRAS, nCAS: multiplex address line row and column selection, only one address line can be used at the same time (either row or column), our board chip has 256M (2^28), 28-3 (bank) -15 (row address) = 10 (column address)
· Addressing process
This operation sequence is, first slice selection, CS pulls low, and then, when RAS pulls low, it means that the line address passed is A0-A14, 15 bits; When the CAS is pulled low, it means that the column address is passed, which is A0-A9, and the more bits of the column address are reserved for expanding the memory, and a chip memory can be extended to 512M.
Memory is divided into multiple banks for reasons
Since DDR does not have its own charging circuit, so, every once in a while, the memory controller will refresh the circuit, that is, to charge once, if there is only one bank, then the result is that at some point, either charge or not charge.
Divided into 8 banks like the above, when I charge 000, I can also read data in 010 or other banks, which reduces the waiting time, needless to say that when the circuit is refreshed, the data cannot be read.
On the exynos board, the size of each bank = 256M/8=32M (2^3 banks on 1 chip)
Memory calculation method
SDRAM capacity calculation
Count the number of addressable units (32 bits)
Number of address lines (number of pins): 11 (A0-A10)
Number of banks: 2(BA0-BA1) 2^2 banks can be combined
Number of large lines = 211 (e.g. number of address lines, 11 pin lines, 211 combinations)
Number of large columns = 211 (e.g. address line number, 11 pin lines, 211 combinations)
Total number of units in a bank = 211x 211
Total number of units in the chip = (number of banks) × (total number of units in a bank)
= 22 x 211 x 211
= 224
Remark:
Because the data transmitted on line-to-column lines is encoded (combined), not directly line and column numbers,
This means that there are 213 rows and 29 columns in each bank, not just 13 rows and 9 columns.
So the unit to be addressed is in row (2 line data), column (2 line data).
For example, bank0, line data is 0 0000 0010 0000, column data is 0 0000 1000,
This means to get the data of the cells of row 32, column 8, not row 5, column 3.
If the line data is 0 0010 1101 0110, and the nomoline data is 0 0011 1010, it means that the data of the cells of row 726 and column 58 is obtained.
For example, a 32MB SDRAM chip has 4 logic-banks, 16 bits wide (that is, 16 bits per cell), 13 address lines, 13 large lines, and 9 large columns. Calculated as:
Number of units in a bank = 213 x 29 = 4194304 (i.e. 4M).
Total number of chip units = 4Banks × 4M units = 16M units.
Total number of chip bits = 16M units × 16bits/per_unit = 256M bits.
Total chip bytes = 256M bits/8 = 32M bytes.
Memory initialization process
On page 1046 of the data sheet "SEC_Exynos4412_Users Manual_Ver.1.00.00" provided by Samsung, there is an initialization step for LPDDR2-S4, LPDDR2 stands for low power DDR2, and the initialization process for DDR3 should be the same as this, and we will initialize DDR3 according to this process
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