The Peking University team has created 90nm carbon nanotube transistors to promote the engineering development of carbon-based chips, and related hydrogen sensor products have been launched

Recently, the team of Academician Peng Lianmao / Professor Zhang Zhiyong of Peking University has created a 90nm carbon nanotube transistor based on array carbon nanotubes, which has the ability to be highly integrated.

Figure | Zhang Zhiyong (Source: Zhang Zhiyong)

This means that carbon nanotube semiconductors have certain application potential in digital integrated circuits at 90nm and below technology nodes, and this also provides insights for further exploration of all-carbon-based integrated circuits.

Regarding the reviewers' comments, "The researchers demonstrated a 6-tube SRAM cell with an area of less than 1 square micron, which is a milestone in new integrated circuit technology. ”

In this study, by using the carbon nanotube array film previously developed by the team, and by reducing the transistor gate length and source-drain contact length, the research group prepared a carbon nanotube transistor with a gate pitch (CGP) of 175nm, with an open-state current of 2.24mA/μm and a peak transconductance gm of 1.64mS/μm. Compared to 45nm silicon-based commercial node devices, the transistor has higher performance.

(Source: Nature Electronics)

Based on this, the team prepared a static random-access memory cell (SRAM) based on industry integration standards, which has an overall area of only 0.976 square microns and contains 6 transistors (6T).

In mainstream digital integrated circuit technology, SRAM cell area is an important parameter to measure the actual integration density. Although a large number of studies have demonstrated 6T SRAM of carbon nanotubes or low-dimensional semiconductor materials, their cell area is much larger than that of SRAM cells at silicon-based 90nm nodes, and the degree of integration still needs to be improved.

For the first time, the research group used non-silicon-based semiconductor materials to create a 6-T SRAM circuit with an overall area of less than 1 square micron, which indicates that carbon-based digital integrated circuits can fully meet the integration needs of 90nm technology nodes.

(Source: Nature Electronics)

On this basis, the team further explored the possibility of carbon-based transistor reduction, demonstrating that carbon-based transistors can be reduced to sub-10nm technology nodes according to strict industrial gate standards.

Considering that when low-dimensional semiconductor devices contact the resistance, the resistance increases sharply with the reduction of the contact length, which will make the overall size of the device unable to be reduced.

To this end, the research group proposed a full-contact structure, combined with the carrier injection mechanism of side contact and end contact, so that the device not only exhibits lower contact resistance, but also has weaker contact length dependence.

Based on the all-contact structure, the team tried to reduce the CGP of carbon transistors to 55nm, which corresponds to the 10nm technology node in silicon-based transistors. At the same time, this carbon transistor outperforms PMOS transistors based on silicon-based 10nm nodes.

(Source: Nature Electronics)

This achievement also demonstrates the advantages of carbon nanotube transistors in performance and integration, combined with its simple process, low power consumption and suitable for single-chip three-dimensional integration, will make carbon nanotube transistor technology play a major advantage in the field of high-performance digital integrated circuits, thus becoming a general chip platform technology, which is expected to be used in high-performance computing, artificial intelligence, broadband communication, intelligent sensing and other fields.

It is understood that the main development of integrated circuits is to improve performance and integration by reducing transistor size, while reducing power consumption and manufacturing costs. In order to continue to promote the development of integrated circuits, the core materials, device structures and system architecture of future electronics have been extensively explored and in-depth researched by the academic community and the industry.

Among them, the most concerned way is to use ultra-thin, high carrier mobility semiconductors to build CMOS (Complementary Metal Oxide Semiconductor) devices including two-dimensional semiconductor materials, one-dimensional semiconductor nanowires and carbon nanotubes, which have better reducibility and higher performance than silicon-based transistors. Therefore, these devices have been used to build nanotransistors.

At present, carbon nanotube transistors have shown their potential to surpass commercial silicon-based transistors and are expected to be used in digital integrated circuit applications.

However, most studies have focused only on the reduction of the gate length of the device and have not really demonstrated the potential of carbon nanotube transistors in terms of integration. The main technical indicators that integrated circuits focus on are multifaceted, including performance, power consumption and integration.

As early as the beginning of 2018, Zhang Zhiyong planned to develop a carbon nanotube CMOS chip process based on the 90nm technology node in accordance with the technology node release standards of the integrated circuit industry.

Zhang Zhiyong said: "To this end, I first investigated the maturity of materials, equipment, and process technology, and then looked for and trained Lin Yanxia, a doctoral student who focused on this direction, and spent a year training Lin Yanxia in device physics and process knowledge. ”

Later, Zhang Zhiyong gave Lin Yanxia a goal: to complete the smallest transistor and integrated circuit units, and use the research equipment of the school laboratory to complete the process that is difficult to complete with the industry's top equipment.

This not only requires Lin Yanxia to have a deep understanding of device physics, but also superb experimental skills, and most importantly, tough quality.

Later, Lin Yanxia did it for five years. "Halfway through the new crown three years, the experiment is intermittent, and she has been on the verge of emotional collapse many times. The most impressive thing was that twice she cried and complained to me: Why did the teacher let me do such a difficult thing? But she persevered and got the job done. Zhang Zhiyong said.

Finally, the paper was published in Nature Electronics as "Scaling aligned carbon nanotube transistors to a sub-10nm node" [1].

Lin Yanxia, a doctoral student at the Institute of Advanced Interdisciplinary Studies of Peking University, and Cao Yu, an associate researcher at the Carbon-based Electronics Research Center of Peking University, are co-authors, and Academician Peng Lianmao and Professor Zhang Zhiyong, from the Institute of Carbon-based Integrated Circuits of Beijing Yuanxin, the School of Electronics of Peking University, and the Carbon-based Electronics Research Center, serve as co-corresponding authors.

Related papers (Source: Nature Electronics)

It is also reported that the highly sensitive carbon nanotube transistor hydrogen sensor product developed by the team has been put on the market, and its detection limit can reach 0.5ppm, which is the highest-end hydrogen sensor product and the world's first carbon nanotube chip product.

Related carbon nanotube biosensing chips are also under development and are expected to be introduced to the market in the next two years for use in food safety, virus detection, early screening of chronic diseases, medical diagnosis and other fields.

However, CMOS transistors are also required to achieve high-performance digital integrated circuits, and this study only shows the size reduction of PMOS transistors and the miniature circuits of full PMOS, so it is necessary to further explore the reduction of NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) transistors to demonstrate the reduction ability of CMOS circuits and static random access memory to achieve 6T CMOS.

The reduction of carbon-based NMOS transistors presents greater challenges than PMOS transistors. The main reason is the source-drain contact of the NMOS device, using the more active metal scandium, which is easily oxidized.

Especially when reduced to a relatively thin line, this will cause the contact resistance of the device to increase dramatically, which in turn will lead to a rapid deterioration of the performance of the device, so it is difficult to reduce the overall size of the carbon tube NMOS transistor to 200nm while maintaining performance.

Therefore, the research group will reduce the carbon tube NMOS device to 10nm and below nodes by adopting a special process, and truly realize the carbon tube CMOS process of the advanced technology node.

In addition, the process currently used by the team is mainly based on laboratories rather than standard industrial techniques. For example, the stripping process widely used in academia can not meet the actual needs of large-scale integrated circuits, so it needs to be replaced by the industry-standard dry etching process.

Therefore, the research group intends to develop a standardized process based on carbon nanotube CMOS transistors and promote the engineering development of carbon-based chips.

So, what is the current development status of carbon nanotube chips? Has it been or is it expected to be commercially available?

Zhang Zhiyong said: "We have mastered the core technology in the field of carbon-based materials and device preparation, and have initially opened up the main links of materials, devices and chip displays, and have future-oriented technology promotion capabilities and equipment upgrade capabilities. ”

Combining the processing and design platforms and technologies of traditional integrated circuits, as well as organizational management experience, it is entirely possible for the team to take the lead in making breakthroughs in the global field.

With the development of carbon-based electronic technology, it is also expected to produce new chip technology and new industrial chains. From the current technology development trend, carbon nanotube chips are in the iterative process of engineering, and a complete technical chain is about to be formed in the future.

However, it will take some time to build a high-end digital integrated circuit, so the method of "laying eggs along the way" can be adopted.

Specifically, carbon-based electronics will be used in the field of sensor chips in the next 3 years or so, and in the field of RF chips in the next 5-8 years or so, and will be used in the field of high-end digital chips in the next 15 years.

By 2037, it is expected to realize the carbon-based 7nm process (equivalent to the silicon-based 2/1nm process), when a complete carbon-based electronics industry ecology will be formed, and carbon-based chips will also be truly used in the field of mainstream high-performance logic chips, so that carbon-based electronic technology can fully surpass traditional semiconductor technology.

Finally, Zhang Zhiyong said: "The future has come, and carbon nanotube chips are about to go out of academic journals and enter our lives. ”

Resources:

1.Lin, Y., Cao, Y., Ding, S. et al. Scaling aligned carbon nanotube transistors to a sub-10nm node. Nature Electronics 6, 506–515 (2023). https://doi.org/10.1038/s41928-023-00983-3