RISC-V is an exciting and rapidly evolving technology. RISC-V is software; It is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. So far, this FAQ series has explored "How RISC-V Evolves and Provides Stability, Scalability, and Security," "Increasing Availability of Tools Reduces the Risk of Using RISC-V," and "RISC V for AI Machines" Learning and Embedded Systems. The final FAQ considers the use of RISC-V in ultra-low-power applications.
Pulp platform
The parallel ultra-low power (PULP) platform was originally a joint effort of ETH Zurich's Integrated Systems Laboratory (IIS) and the Energy Efficient Embedded Systems (EEES) group at the University of Bologna to explore new and efficient architectures for ultra-low power consumption. Low-power processing.
The PULP platform family includes single-core, multi-core and multi-cluster solutions (Image: PULP Platform)
PULP is developing an open, scalable hardware and software R&D platform to break down barriers to energy efficiency in the power range of a few milliwatts and meet the computing needs of IoT applications that need the flexibility to handle data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, and vital signs monitors. Pulp features:
- Efficient implementation of RISC-V cores. These include: 32-bit Level 4 Core CV32E40P (formerly RI5CY), 64-bit Level 6 CVA6 (formerly Ariane), 32-bit Level 2 Ibex (formerly known as Zero Risk)
- The complete system is based on: single-core microcontrollers (PULPissimo, PULPino), multi-core IoT processors (OpenPULP), multi-cluster heterogeneous accelerators (Hero)
- The open source SolderPad license is a perpetual, worldwide, non-exclusive, free, royalty-free, irrevocable license
- Abundant peripherals I2C, SPI, HyperRAM, GPIO
PULP includes state-of-the-art microcontroller systems and multicore platforms that deliver leading energy efficiency and widely adjustable performance. Compared to single-core microcontroller units, parallel ultra-low-power programmable architectures can meet the computing requirements of IoT applications without exceeding the power envelope of a few milliwatts typical of small battery-powered systems.
PULP is an open source platform. TO DATE, PULP HAS RELEASED EFFICIENT 32-BIT AND 64-BIT IMPLEMENTATIONS BASED ON THE OPEN SOURCE RISC-V INSTRUCTION SET ARCHITECTURE, PERIPHERALS, AND COMPLETE SYSTEMS, FROM SIMPLE MICROCONTROLLERS TO STATE-OF-THE-ART OPENPULP VERSIONS, A NEW BENCHMARK FOR LOW-POWER MULTICORE IOT PROCESSORS. In addition, PULP is designed to support multiple application programming interfaces, such as OpenMP, OpenCL, and OpenVX, allowing flexible application porting, development, performance tuning, and debugging.
PULP platform processor
Several companies offer processors based on the open source PULP platform. GreenWaves Technologies offers ultra-low-power and high-performance GAP8 APs that enable AI in battery-powered IoT devices. GreenWaves is a major contributor to RISC-V's RISC-V-based PULP open source platform that laid the foundation for its GAP8 processor. GAP8 is an IoT application processor that enables large-scale deployment of low-cost, battery-powered smart devices that capture, analyze, classify, and act on the fusion of rich data sources such as images, sound, radar signatures, and vibration.
Greenwave Technologies' GAP8 functional block diagram. (Image source: Greenwave Technology)
GAP8 is optimized to perform a wide range of image and audio algorithms, including highly energy-efficient convolutional neural network inference and signal processing. GAP8 allows industrial and consumer product manufacturers to integrate signal processing, artificial intelligence, and advanced classification into new battery-powered wireless edge devices for IoT applications, including image recognition, people and object counting, machine health monitoring, home security, voice recognition, audio enhancement, consumer robotics, and smart toys.
The latest version of Renode, Antmicro's open-source multi-node emulation framework, adds support for more RISC-V platforms and CPUs, including VEGAboard with RI5CY, a 32-bit RISC-V kernel originally created for the PULP platform. Renode's board support includes UART and timer models as well as the Digilent Arty FPGA evaluation kit with LiteX and VexRiscv, which is the goal of getting started with LiteX build environments.
LiteX in Renode supports further upgrades to SPI, control and status, SPI flash, and GPIO port peripheral models. LiteX is Antmicro's choice for vendor-neutral, Linux and Zephyr-enabled soft SoC platforms that can support many internal and external use cases. Version 1.8 also adds support for Minerva, a 32-bit RISC-V soft CPU, which is now also available as an option for LiteX SoCs.
Non-PULP low-power RISC-V processor
Not surprisingly, given RISC-V's modularity and extensibility, there have been many independent efforts to develop low-power RISC-V processors and extensions to RISC-V ISA. An example of the latter is a demonstration by Codasip using the company's Codasip Studio to develop an RISC-V ISA extension for ultra-low-power IoT wireless signal processing. The resulting ISA extension is implemented on Codasip Bk3, which has a single 3-stage pipeline architecture that provides a good balance between low power consumption and performance up to 3.1 CoreMark/MHz.
The goal of the Codasip project is to develop a simple ISA extension to support multiple wireless protocols without increasing the power consumption of the BK3 processor. The project resulted in an ISA with 13 directives. It achieves zero incremental energy costs, has efficient automatic gain control, and has been demonstrated on Bluetooth, Sigfox, and LoRa wireless devices.
Huami recently launched a new artificial intelligence chip for wearable devices. Huami Huangshan-2 (MHS002) is based on the RISC-V architecture and is expected to enter mass production in the fourth quarter of 2020. The first wearable device with the chip will be available in 2021.
Huami said that the new chip is faster and more energy-efficient than the previous generation of chips, and the overall power consumption is reduced by 50%. The energy improvement is achieved with the help of always-on sensor mode and the C2 coprocessor. Huangshan 2 was listed about a year and a half more than Huangshan 1, which has a cardiac biometric engine, electrocardiogram, ECG Pro and engine to monitor heart rhythm abnormalities.
Telling Semiconductor and Andesian Technology recently launched a new system-on-chip (SoC) for Tailing's latest product line, the TLSR9 series. Powered by the 32-bit AndesCore D25F, the TLSR9 series is designed for next-generation hearables, wearables, and high-performance IoT applications. Thanks to the two companies' partnership with IAR Systems, IoT designers can also use IAR's Embedded Workbench (EW), a powerful development toolchain that supports flexible product development.
The Telink TLSR9 series is the latest addition to Telink's complete family of connectivity solutions designed to maximize equipment performance and reduce time to market. The TLSR9 family is designed with AndeStar™ V5 instruction set architecture (ISA) and complies with the latest RISC-V technology.
Powered by a D25F RISC-V processor, the TLSR9 SoC is the world's first RISC-V DSP/SIMD P expansion designed for a variety of mainstream audio, wearable, and IoT development needs. The D25F has an efficient five-stage pipeline that delivers 2.59 DMIPS/MHz and 3.54 CoreMark/MHz performance. By supporting RISC-VP Scaling (RVP), the D25F significantly improves the efficiency of small-volume data calculations and enables compact AI/ML applications on edge devices.
The MAX78000 combines convolutional neural networks and RISC-V cores with an Arm Cortex processor. (Image source: Maxim Integrated Products)
Maxim Integrated Products' MAX78000 low-power neural network acceleration microcontroller combines a convolutional neural network (CNN) and RISC-V core with an Arm Cortex processor. This combination of capabilities pushes AI to the edge without impacting the performance of battery-powered IoT devices. Performing AI inference at less than 1/100th the energy consumption of software solutions can significantly improve the uptime of battery-powered AI applications while supporting complex new AI use cases.
At the heart of the MAX78000 is dedicated hardware designed to minimize CNN power consumption and latency. The hardware operates with minimal microcontroller core intervention, simplifying operation. To efficiently feed data from the outside world into the CNN engine, customers can use one of two integrated microcontroller cores: the ultra-low-power Arm Cortex-M4 core or the lower-power RISC-V core.
RISC-V is evolving and provides stability, scalability, and security. This series of FAQs discusses how RISC-V has become more commercially attractive due to recent developments in design and verification tools. The selection of RISC-V-based devices optimized for specific applications such as IoT and wearables, embedded systems, artificial intelligence, machine learning, virtual reality, augmented reality, and military and aerospace systems is also increasing. RISC-V is an emerging technology that most designers should follow and become increasingly familiar with.