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Chat with ChatGPT to solve a major problem in the CPU development process?
Researchers at New York University (NYU) accomplished something that seemed impossible:
No need for specialized hardware description language (HDL), you can design chips just by speaking human language!
With the help of ChatGPT, they not only designed a component on the CPU, but even passed the validity verification process.
This component is primarily responsible for creating the logic of an eight-bit accumulator-based microprocessor architecture. The accumulator is essentially a register (memory), which is dedicated to storing an operand of arithmetic or logical operations and storing the results of the operation. This is an integral part of CPU operation.
So, what else can't big language models do?
Some netizens said:
Automating part of the chip design process is good news.
Some netizens have also expressed concerns about the use of AI to write HDL in chip design:
What does ChatGPT do with chip design?
Typically, there are several stages in the process of designing and manufacturing chips.
One of these stages is to use Hardware Description Language (HDL) (e.g. Verilog) to describe the actual geometry, density, and overall layout of the different parts within the chip.
Previously, HDL writing as an extremely specialized and complex field has been a relatively rare and very difficult job to master.
Dr. Hammond Pearce, one of the research team members and a research assistant professor, said:
The biggest challenge with hardware description languages is that not many people know how to write them, and it's hard to be an expert in them.
This means that even the best engineers often need to do trivial things in this language.
As a pattern recognizer, ChatGPT can easily switch between various types of languages, which can help engineers skip the HDL stage.
△Design flow for creating ICs (integrated circuits) using LLM.
In this study, the researchers used LLM to examine eight representative hardware design examples. Engineers interact back and forth with LLM in real time, gradually translating plain English text into Verilog (HDL) equivalents.
One of the hardware engineers worked with LLMs to design a novel eight-bit accumulator-based microprocessor architecture. They sent these benchmarks and processors to Skywater 130nm Shuttle for tapeout.
In this process, the researchers evaluated the Verilog ability of four different LLMs: ChatGPT-4, ChatGPT-3.5, Bard, and HuggingChat:
In addition, the researchers benchmarked against the 8-bit shift register. Tells the large model that it is trying to create a Verilog model for a "test name". It then provides a specification description, defines the input and output ports, and other specific information required. Finally, ask him how he can write a design that meets these specifications.
△Design tips for 8-bit shift registers
Here are the design options given by different large models:
The figure on the left is the eight-bit shift register design of ChatGPT-4, and the figure on the right is ChatGPT-3.5
△ The image on the left is Bard (the "red" input in line 4 is too wide), and the picture on the right is HuggingChat (truncated, formatted)
As the chart above shows, while ChatGPT both met the specifications and began the design process, neither Bard nor HuggingChat met the initial criteria for the specifications.
The researchers regenerated responses five more times based on the initial prompts from Bard and HuggingChat, but both failed. Bard has not been able to meet the given design specifications, and HuggingChat's Verilog output does not conform to the syntax specification after the module is defined.
Given that Bard and HuggingChat performed poorly on the initial challenge benchmark, the researchers decided that the follow-up full test would only be performed on ChatGPT-4 and ChatGPT-3.5.
At the same time, by the way, let the large model carry out the design of the Testbench:
Can you write a Verilog testbed for this design? The test bench should have self-test capability and be able to be used with Iverilog for simulation and verification. If a test case fails, the test bench should be able to provide enough information to find and resolve the error.
The final results showed that ChatGPT-4 performed better. Most benchmarks pass, and most only require tool feedback.
ChatGPT-4 has more difficulty creating a workable test bench than creating a runnable design, often requiring human feedback.
Compared to ChatGPT-4, ChatGPT-3.5 performed significantly poorly, with most benchmarks failing, and most of those conversations that passed the test bench did not meet the specifications. Compared to ChatGPT-4, ChatGPT-3.5 presents a wide variety of issues between each conversation and benchmarks, requiring more frequent corrections in terms of design and test benches.
ChatGPT is a "force multiplier" in chip design
As the Big Language Model (LLM) continues to evolve, LLM may be easily implemented in the future, from conception to functional design.
△ The accumulator-based data path designed by the researchers using ChatGPT-4 (the figure is drawn by humans), and the control signals are represented by dashed lines
According to the researchers:
While we emphasize the single-step performance of models (i.e., one-step design), hardware applications may perform better by having them on board as "co-designers."
When working with experienced engineers, they can be a kind of "force multiplier." Engineers can fine-tune and iterate quickly based on the "first version of the design" provided by the model.
Dr Hammond Pearce said:
This study is what we believe is the first case of a hardware description language (HDL) generated entirely by AI to be translated into a physical chip. Some AI models, such as OpenAI's ChatGPT and Google's Bard, can generate software code in different programming languages, but their application in hardware design has not been widely studied.
This study shows that AI also has potential in hardware manufacturing, especially in conversational applications, where design can be perfected through repeated communication.
And as a result, there are fewer human-induced errors in HDL writing, which shortens design time and time to market, and allows for more creative designs.
I wonder if some HDL engineering experts will feel a little nervous when they hear this.
The researchers believe that if this process can be automated, it will not only speed up the current work, but also alleviate artificial bottlenecks. However, there are risks associated with relying solely on large models like ChatGPT, or software machines that rely on electricity to run. LLM for chip design also has a series of problems such as difficult black boxes in the training stage.
What is your opinion on this?
Reference Links:
[1] https://arxiv.org/abs/2305.13243 (link to paper)
[2]https://www.tomshardware.com/news/conversation-with-chatgpt-was-enough-to-develop-part-of-a-cpu
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