laitimes

The price of 3nm process foundry has broken a new high, how to ensure high-quality chips?

author:Chip failure analysis

Failure Analysis Zhao Gong Semiconductor Engineer 2023-01-16 08:48 Posted in Beijing

Following the official announcement of Samsung Electronics on June 30, 2022 to start mass production of 3nm chips based on GAA transistor structure, TSMC also held a high-profile 3nm mass production expansion ceremony in Tainan Science Park at the end of 2022, which means that the two major players in the advanced process have reached the mass production conditions of the 3nm process. However, the foundry price of advanced processes is not low, according to industry sources, the foundry price of 3nm processes has exceeded $20,000 per wafer, which means that chip manufacturers need to spend nearly 140,000 yuan to process a 12-inch wafer and produce hundreds of chips.

In addition to the high price, the number of transistors on the same chip under advanced process nodes will increase exponentially, which will inevitably lead to a series of problems such as increased manufacturing process variability, in this case, how should chip developers ensure the quality, safety and reliability of chips? The traditional chip development process solves all design problems at the tape out stage, but in today's increasingly complex designs, this approach is a bit lagging behind, so a new solution is needed to optimize each link by connecting and integrating key data at each stage to achieve detailed analysis and management of the chip and system lifecycle, so as to optimize each link to ensure the desired results.

Continuous optimization of chips and end systems from PLM to SLM

For decades, companies across industries have used product lifecycle management (PLM) tools to manage their products from early production to market deployment. Since the 50s of last century, semiconductor chips have been closely related to our daily lives. In the process of this digital revolution, there are no products similar to PLM that provide more specialized lifecycle management for semiconductor products. It is only in recent years that the concept of chip management process------ Silicon Lifecycle Management (SLM) has begun to emerge and gradually gained industry recognition.

Synopsys provides integrated solutions for hardware and software products, simulation tools, data integration, and analysis from semiconductor product software and hardware development, design simulation, product manufacturing, and even In-Field applications. The result is a complete SLM platform throughout the product lifecycle.

In fact, SLM is based on the concept of PLM product lifecycle management, Dr. Paul Simon, director of R&D and operations of Synopsys' EDAG business group, data analysis department, said in an interview that Synopsys' strategy is to connect the large amount of data generated at each stage of chip design, verification test, manufacturing and deployment, and integrate it into the same cloud system database, which can collect and analyze this data to improve chip performance, speed, mass production yield, Important core indicators such as quality control and time to market to enhance the overall value of chip products.

Of course, through the detection and analysis of the SLM platform, chip developers can continuously optimize the chip and end-user system based on the analysis results.

Through continuous intelligent analysis of quality, the operation status indicators of the entire chip product life cycle can be effectively improved.

The SLM process consists of the following two main stages:

  • IP such as sensors and monitors is added to the chip design process to provide a large amount of chip data generated in the design process, so that the equipment production and actual performance can be analyzed in depth
  • Efficient product data analysis database and platform collects, processes and analyzes various types of data across all stages of the product life cycle, supporting design, production and customer site optimization

At the beginning of the SLM process, hardware such as key PVT monitors and structural sensors are added, which are basically the eyes, ears, and senses of the device, providing developers with extremely high visibility of chip data.

Next, these extracted chip data are used to calibrate the parameters of the design model; Measurements such as ring oscillators, critical circuit path test results, and process/voltage/temperature (PVT) monitor data. These data collection tools combine raw data with intelligent integrated automation to provide the system with targeted analysis of each life stage of the chip, and developers can optimize each design stage based on the analysis.

In other words, with SLM, developers can efficiently implement the concept of "observe, control and optimize". Real-time data and parameters collected and fed back by embedded monitors and sensors translate directly into improvements in the quality, performance, and reliability of the system-on-chip.

SLM is also able to predict product maintenance and failure conditions in use, so it is increasingly used in applications such as hyperscale data centers, consumer electronics, and automotive

Benefits of SLM

Using the proven SLM platform, silicon developers can achieve deep lifecycle visibility, obtain full analysis results, and improve control mechanisms for chip devices, including dynamic voltage frequency scaling (DVFS). Together, these features greatly optimize power device operation and data throughput.

However, it is important to note that end-to-end lifecycle management is not possible by deploying a single product or tool, so it is necessary to integrate various SLM components to ensure that the benefits of a particular application are realized. For example, high-volume consumer applications can leverage SLM tools and processes to reduce the impact of design constraints by referring to chip parameter feedback. This allows design adjustments to be made to improve visibility into statistical anomalous data and potentially failed devices in the future.

In real-time system management, high-particle thermal sensing solutions can optimize power performance for very large-scale data applications if deployed throughout the on-chip processor core. This is especially critical for hyperscale data applications, where even the slightest reduction in power consumption can have an exponential impact on large cloud server configurations. A small improvement in thermal sensing accuracy could reduce power consumption by less than a cent per hour per processor chip. While it may not seem obvious at the chip level, such small optimizations can save millions of dollars a year for large data center configurations. Given that the cost of running a server over its lifetime is higher than the initial purchase price, any magnitude reduction in power consumption makes sense.

In automotive applications, continuous assessment of aging and deterioration factors, such as user conditions, thermal stress, and supply voltage stress, will provide a more predictive approach to the maintenance and update of in-vehicle electronic systems. If these systems are more predictive of failure, consider using commercial-grade chips in the design to reduce costs and improve determinism.

With the introduction of AI, SLM accelerates chip design

Visibility into chip data is extremely important for developers, and as mentioned earlier, if you want to get more data, you need to integrate various SLM components, and Synopsys offers an SLM platform that optimizes chip conditions at all stages of the chip lifecycle. It includes several integrated solutions and features:

  • A wide range of metrics, monitoring IP, and access infrastructure can collect all aspects of chip operation data. Indicator monitoring includes environmental, structural monitors, and test structures
  • A comprehensive inspection integration and validation process that connects directly to Synopsys' Fusion RTL to GDSII implementation systems
  • Semiconductor manufacturing analysis engine and yield management engine to optimize operational efficiency and improve overall yield
  • Autonomously optimize the platform to automatically improve computing system performance in real time

In order to improve its SLM platform strategy, Synopsys has completed important technology acquisitions in the past three years, including on-chip monitoring PVT sensors, post-silicon big data analysis platform, and real-time field optimization technology. At the same time, by integrating SLM with EDA and IP technology, a complete integrated platform has been built to provide a massive data analysis engine and high-speed data visualization, analysis and modeling functions, so that chip design and product engineering teams can solve important core issues more efficiently and quickly, and grasp the time to market of key products.

As we all know, the chip manufacturing process of advanced processes is very complex, which requires the effective connection of large amounts of data between different process nodes and different fabs, and the technical challenges are great. Synopsys added the acquired SiliconDash technology to the SLM product platform, enabling the efficient integration of diversified and multi-dimensional mass production data across the product manufacturing data chain in SLM. On this basis, it helps product mass production data analysis, product traceability, automatic early warning and control schemes. Provide services for product quality, output and other operation management for mass production. At the same time, artificial intelligence technologies such as edge computing data and machine learning based on real time are used to quickly connect data and transform it into effective analysis decisions and actions, accelerating chip design.

epilogue

SLM gives a whole new direction in chip design and maintenance! It is suitable for different stages of the chip life cycle, from early design, verification, manufacturing production, testing, debugging and product real-life to field operation. Synopsys' SLM platform can monitor and track the operating status of the chip throughout its lifecycle by analyzing the data of on-chip monitors and sensors, so that each stage can be continuously optimized.

In the future, developers can use SLM to track how their designs perform in different devices and continuously optimize their chips and end products through the data collected, and it can be said that SLM is likely to change the game in the entire field of advanced process design.

Source: eEnthusiast Network

The price of 3nm process foundry has broken a new high, how to ensure high-quality chips?

Semiconductor Engineer

Semiconductor experience sharing, semiconductor achievement exchange, semiconductor information release. Semiconductor industry dynamics, semiconductor practitioner career planning, chip engineer growth process.