import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
(new chisel3.stage.ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => new FullAdder)))
common options
-tn, --top-name <top-level-circuit-name>
This options defines the top level circuit, defaults to dut when possible
-td, --target-dir <target-directory>
This options defines a work directory for intermediate files, default is .
-ll, --log-level <Error|Warn|Info|Debug|Trace>
This options defines a work directory for intermediate files, default is .
-cll, --class-log-level <FullClassName:[Error|Warn|Info|Debug|Trace]>[,...]
This options defines a work directory for intermediate files, default is .
-ltf, --log-to-file default logs to stdout, this flags writes to topName.log or firrtl.log if no topName
-lcn, --log-class-names shows class names and log level in logging output, useful for target --class-log-level
--help prints this usage text
<arg>... optional unbounded args
chisel3 options
-chnrf, --no-run-firrtl Stop after chisel emits chirrtl file
firrtl options
-i, --input-file <firrtl-source>
use this to override the default input file name , default is empty
-o, --output-file <output>
use this to override the default output file name, default is empty
-faf, --annotation-file <input-anno-file>
Used to specify annotation files (can appear multiple times)
-foaf, --output-annotation-file <output-anno-file>
use this to set the annotation output file
-X, --compiler <high|middle|low|verilog|sverilog>
compiler to use, default is verilog
--info-mode <ignore|use|gen|append>
specifies the source info handling, default is append
-fct, --custom-transforms <package>.<class>
runs these custom transforms during compilation.
-fil, --inline <circuit>[.<module>[.<instance>]][,..],
Inline one or more module (comma separated, no spaces) module looks like "MyModule" or "MyModule.myinstance
-firw, --infer-rw Enable readwrite port inference for the target circuit
-frsq, --repl-seq-mem -c:<circuit>:-i:<filename>:-o:<filename>
Replace sequential memories with blackboxes + configuration file
-clks, --list-clocks -c:<circuit>:-m:<module>:-o:<filename>
List which signal drives each clock of every descendent of specified module
-fsm, --split-modules Emit each module to its own file in the target directory.
--no-check-comb-loops Do NOT check for combinational loops (not recommended)
--no-dce Do NOT run dead code elimination
chisel3.Driver.execute(Array("--target-dir", "generated"), () => new FullAdder)
(new chisel3.stage.ChiselStage).emitVerilog(new FullAdder, Array("--target-dir", "generated"))
(new chisel3.stage.ChiselStage).execute(Array("--target-dir", "generated"), Seq(ChiselGeneratorAnnotation(() => new FullAdder)))
val my_arg = Array("8","--target-dir", "generated")
(new chisel3.stage.ChiselStage).emitVerilog(new Adder(my_arg(0).toInt),my_arg)
(new chisel3.stage.ChiselStage).execute(my_arg, Seq(ChiselGeneratorAnnotation(() => new Adder(my_arg(0).toInt))))
錯誤寫法
(new chisel3.stage.ChiselStage).emitVerilog(new Adder(Array(0).toInt),Array("8","--target-dir", "generated"))
(new chisel3.stage.ChiselStage).execute(Array("--target-dir", "generated"), Seq(ChiselGeneratorAnnotation(() => new Adder(Array(0).toInt))))
// addertest.scala
package test
import scala.util._
import chisel3.iotesters._
class AdderTest(c: Adder) extends PeekPokeTester(c) {
val randNum = new Random
for(i <- 0 until 10) {
val a = randNum.nextInt(256)
val b = randNum.nextInt(256)
poke(c.io.a, a)
poke(c.io.b, b)
step(1)
expect(c.io.s, (a + b) & 0xff)
expect(c.io.cout, ((a + b) & 0x100) >> 8)
}
}
// addertest.scala
package test
//特質ChiselScalatestTester在該包下，并且定義了需要使用的test方法
import chiseltest._
//FlatSpec在該包下
import org.scalatest._
class AdderTest extends FlatSpec with ChiselScalatestTester{
behavior of "MyModule"
// test class body here
it should "do something" in {
//test case body here
test(new Adder(8)) { c =>
//test body here
val randNum = new Random
for(i <- 0 until 10) {
val a = randNum.nextInt(256)
val b = randNum.nextInt(256)
c.io.a.poke(a.U)
c.io.b.poke(b.U)
c.clock.step(1)
c.io.s.expect(((a + b) & 0xff).U)
c.io.cout.expect((((a + b) & 0x100) >> 8).U)
}
}
}
}
test Adder Success: 20 tests passed in 15 cycles in 0.047415 seconds 316.36 Hz
[info] [0.025] RAN 10 CYCLES PASSED
[success] Total time: 7 s, completed Feb 23, 2019 3:13:26 PM
2、運作
chiseltest
寫的測試
在使用
chiseltest
的代碼中，如果
AluTester
繼承了
FlatSpec
，那麼即使定義成了
class
（正常情況下，在
scala
中主函數必須定義在
object
中），該段代碼還是可以運作，隻不過運作方式和之前不一樣了，寫法如下：
如果想要生成vcd檔案，寫法如下：
注意此時不能使用
test:runMain
來運作了，因為隻有定義成
object
才可以這樣被運作，
class
不行。但是如果還想這樣運作，那就必須改成如下形式：
package test
//特質ChiselScalatestTester在該包下，并且定義了需要使用的test方法
//peek poke等方法也定義在了該包下，并且定義了隐式轉換，是以我們可以直接.xxxx調用
import chiseltest._
import chiseltest.RawTester.test
object AdderTest extends App{
//test case body here
test(new Adder(8)) { c =>
//test body here
......
}
}
然後在指令行執行以下指令即可：
注意，不能簡單的隻将
class
修改為
object
，然後再混入
App
。因為這樣雖然不報錯，但是好像不工作。如下所示：
package test
//特質ChiselScalatestTester在該包下，并且定義了需要使用的test方法
//peek poke等方法也定義在了該包下，并且定義了隐式轉換，是以我們可以直接.xxxx調用
import chiseltest._
//FlatSpec在該包下
import org.scalatest._
object AdderTest extends FlatSpec with ChiselScalatestTester with App{
behavior of "MyModule"
// test class body here
it should "do something" in {
//test case body here
test(new Adder(8)) { c =>
//test body here
......
}
}
}
