提升PendSV中斷的優先級

設定外設的中斷優先級可以用STM32提供的庫。

 如：

NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
           

但對于系統内部異常的優先級的設定，我還沒有找到相應的庫函數。

但是，在《Cortex M3技術參考》文檔中找到相關的寄存器。

8.2.2 NVIC register descriptions

    System Handler Priority Registers ， Address  0xE000ED18, 0xE000ED1C , 0xE000ED20

Use the three System Handler Priority Registers to prioritize the following system handlers :

• memory manage
• bus fault
• usage fault
• debug monitor
• SVC
• SysTick
• PendSV

在uCOS在STM32的移植檔案中 os_cpu_asm.asm 用到對該寄存器的操作。

NVIC_INT_CTRL   EQU     0xE000ED04    ; Interrupt control state register.
NVIC_SYSPRI14   EQU     0xE000ED22    ; System priority register (priority 14).
NVIC_PENDSV_PRI EQU           0xFF    ; PendSV priority value (lowest).
NVIC_PENDSVSET  EQU     0x10000000    ; Value to trigger PendSV exception.

OSStartHighRdy
    LDR     R0, =NVIC_SYSPRI14        ; Set the PendSV exception priority
    LDR     R1, =NVIC_PENDSV_PRI
    STRB    R1, [R0]

    MOVS    R0, #0                    ; Set the PSP to 0 for initial context switch call
    MSR     PSP, R0

    LDR     R0, =OSRunning            ; OSRunning = TRUE
    MOVS    R1, #1
    STRB    R1, [R0]

    LDR     R0, =NVIC_INT_CTRL        ; Trigger the PendSV exception (causes context switch)
    LDR     R1, =NVIC_PENDSVSET
    STR     R1, [R0]

    CPSIE   I                         ; Enable interrupts at processor level

OSStartHang
    B       OSStartHang               ; Should never get here
           

将：

    NVIC_PENDSV_PRI EQU 0xFF

替換為：

    NVIC_PENDSV_PRI EQU 0x00