SSC - Spread Spectrum Clocking 擴頻時鐘技術主要是用來降低EMI。
CC - Common Clocked architectures (CC)
SRIS - Separate Refclk Independent SSC.
SRNS - Separate Refclk with No SSC。
SRNS允許600ppm,而SRIS允許5600ppm(其中SSC允許5000ppm(單向展頻0.5%,0.5/100=0.005*100 0000ppm=5000ppm),TX/RX允許600ppm)
如果使用SSC所有使用SSC晶片的時鐘必須同源
如果不使用SSC,各晶片的時鐘不要求同源
PPM計算方法:
ppm是百萬分之一,我用的晶振是74.25MHz,實際用頻率計測量是74.24MHz,晶振的誤差是(74.24-74.25)/74.25≈0.000135=135*10^-6
誤差是135ppm
HBW_BYPASS_LBW
In PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs.