最近在17.04上安裝OAI ALL IN ONE ，UHD安裝後USRP B210連接配接總是報錯，如下：
[email protected]:~/uhd/host/build$ uhd_find_devices
linux; GNU C++ version 6.2.0 20161027; Boost_106200; UHD_003.009.005-0-unknown
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
type: b200
name: 2000501894107
serial: 30AA06B
product: B210
[email protected]:~/uhd/host/build$ uhd_usrp_probe
linux; GNU C++ version 6.2.0 20161027; Boost_106200; UHD_003.009.005-0-unknown
-- Detected Device: B210
-- Operating over USB 3.
Error: RuntimeError: Expected FPGA compatibility number 13, but got 14:
The FPGA build is not compatible with the host code build.
Please run:
"/usr/lib/x86_64-linux-gnu/uhd/utils/uhd_images_downloader.py"
出現上面錯誤是驅動未安裝好導緻的，首先解除安裝之前安裝的UHD驅動，
[email protected]:~/uhd/host/build$ sudo make uninstall
-- Uninstalling "/usr/share/doc/uhd/README.md"
-- Uninstalling "/usr/share/doc/uhd/LICENSE"
-- Uninstalling "/usr/lib/pkgconfig/uhd.pc"
-- Uninstalling "/usr/lib/cmake/uhd/UHDConfig.cmake"
......
......
......
按照官網源碼安裝法：
https://kb.ettus.com/Building_and_Installing_the_USRP_Open-Source_Toolchain_(UHD_and_GNU_Radio)_on_Linux
[email protected]:~/uhd/host/build$ cmake ../
-- The CXX compiler identification is GNU 6.3.0
-- The C compiler identification is GNU 6.3.0
-- Check for working CXX compiler: /usr/bin/c++
-- Check for working CXX compiler: /usr/bin/c++ -- works
......
......
......
[email protected]:~/uhd/host/build$ make
[ 0%] Generating /home/nano/uhd/host/build/lib/transport/vrt_if_packet.cpp
[ 0%] Generating /home/nano/uhd/host/build/lib/ic_reg_maps/adf4350_regs.hpp
[ 1%] Generating /home/nano/uhd/host/build/lib/ic_reg_maps/adf4351_regs.hpp
[ 1%] Generating /home/nano/uhd/host/build/lib/ic_reg_maps/max2870_regs.hpp
......
.......
[100%] Built target doxygen_docs
[email protected]:~/uhd/host/build$ make test
Running tests...
Test project /home/nano/uhd/host/build
Start 1: addr_test
1/32 Test #1: addr_test ........................ Passed 0.06 sec
[email protected]:~/uhd/host/build$ sudo make install
[email protected]:~/uhd/host/build$ sudo ldconfig
[email protected]:~/uhd/host/build$ uhd_find_devices
linux; GNU C++ version 6.3.0 20170406; Boost_106200; UHD_003.010.001.HEAD-0-g929e3b32
UHD Warning:
EnvironmentError: IOError: Could not find path for image: usrp_b200_fw.hex
Using images directory: <no images directory located>
Set the environment variable 'UHD_IMAGES_DIR' appropriately or follow the below instructions to download the images package.
Please run:
"/usr/local/lib/uhd/utils/uhd_images_downloader.py"
No UHD Devices Found
[email protected]:~/uhd/host/build$ sudo /usr/local/lib/uhd/utils/uhd_images_downloader.py
Images destination: /usr/local/share/uhd/images
Downloading images from: http://files.ettus.com/binaries/images/uhd-images_003.010.001.000-release.zip
Downloading images to: /tmp/tmpEUaJQY/uhd-images_003.010.001.000-release.zip
57832 kB / 57832 kB (100%)
Images successfully installed to: /usr/local/share/uhd/images
[email protected]:~/uhd/host/build$ uhd_usrp_probe
linux; GNU C++ version 6.3.0 20170406; Boost_106200; UHD_003.010.001.HEAD-0-g929e3b32
-- Loading firmware image: /usr/local/share/uhd/images/usrp_b200_fw.hex...
-- Detected Device: B210
-- Loading FPGA image: /usr/local/share/uhd/images/usrp_b210_fpga.bin... done
-- Operating over USB 3.
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize CODEC control...
-- Initialize Radio control...
-- Performing register loopback test... pass
-- Performing register loopback test... pass
-- Performing CODEC loopback test... pass
-- Performing CODEC loopback test... pass
-- Setting master clock rate selection to 'automatic'.
-- Asking for clock rate 16.000000 MHz...
-- Actually got clock rate 16.000000 MHz.
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
_____________________________________________________
/
| Device: B-Series Device
| _____________________________________________________
| /
| | Mboard: B210
| | revision: 4
| | product: 2
| | serial: 30AA06B
| | name: 2000501894107
| | FW Version: 8.0
| | FPGA Version: 14.0
| |
| | Time sources: none, internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX DSP: 0
| | |
| | | Freq range: -8.000 to 8.000 MHz
| | _____________________________________________________
| | /
| | | RX DSP: 1
| | |
| | | Freq range: -8.000 to 8.000 MHz
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | _____________________________________________________
| | | /
| | | | RX Frontend: A
| | | | Name: FE-RX2
| | | | Antennas: TX/RX, RX2
| | | | Sensors: temp, rssi, lo_locked
| | | | Freq range: 50.000 to 6000.000 MHz
| | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB
| | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Frontend: B
| | | | Name: FE-RX1
| | | | Antennas: TX/RX, RX2
| | | | Sensors: temp, rssi, lo_locked
| | | | Freq range: 50.000 to 6000.000 MHz
| | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB
| | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: B210 RX dual ADC
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX DSP: 0
| | |
| | | Freq range: -8.000 to 8.000 MHz
| | _____________________________________________________
| | /
| | | TX DSP: 1
| | |
| | | Freq range: -8.000 to 8.000 MHz
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | _____________________________________________________
| | | /
| | | | TX Frontend: A
| | | | Name: FE-TX2
| | | | Antennas: TX/RX
| | | | Sensors: temp, lo_locked
| | | | Freq range: 50.000 to 6000.000 MHz
| | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB
| | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Frontend: B
| | | | Name: FE-TX1
| | | | Antennas: TX/RX
| | | | Sensors: temp, lo_locked
| | | | Freq range: 50.000 to 6000.000 MHz
| | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB
| | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: B210 TX dual DAC
| | | | Gain Elements: None
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