Verifying today’s complex designs is time consuming, as simulations run for long time and millions of transaction are executed. Traditional approach of debug is to dump all the information of millions of packets in a log file, however it would always be challenging to filter out specific transactions from the huge log file. For example, in case of AXI Protocol, a fixed number of outstanding transactions are allowed during simulation, it would always be difficult to find out such outstanding transaction in the huge log file of a single run of simulation or during interactive simulation. It is one of the biggest pain point of debugging.
Synopsys Verdi protocol analyzer supports unique search/filter capability to overcome such debug pain points. Let’s put some light on, what are the outstanding transactions, with the help of following diagram.
AXI Outstanding Transactions
AXI master can issue multiple address (A1,A2,A3) for read/write without waiting for respective completions. A typical debug requirement is to count and track outstanding transactions in a certain time window of the simulation. Traditional way of debugging through signal dump or log file is very tedious and time consuming.
Verdi protocol analyzer is natively integrated with AXI VIP to make debug easy and fast. A snapshot of the protocol analyzer GUI is shown below. Master/Slave transactions and its properties can be highlighted in the GUI. Search engine can be invoked from a menu button in the tool bar. Using the search engine with appropriate query will filter such transaction in less than 10 seconds making it easy and fast to debug AXI outstanding transactions.
Verdi Protocol Analyzer
The complete solution is described in a white paper – Finding Outstanding Transactions.
Authored by Abhishek Upadhyay
This post is filed under AMBA, Debug, Interconnects.