u-boot起來之後，準備測試下闆上的外設，包括CCSR，PCIE ，CPLD空間能否正常通路，因為phy的解複位由CPLD完成，是以CPLD 必須正常通路，而實際測試過程中發現CPLD無法正常通路。
Cpld位址為ffd00000
- boot下通路直接導緻u-boot重新開機
提示錯誤如下：
=> md 0xffd00000
ffd00000:Machine check in kernel mode.
Caused by (from mcsr): mcsr = 0x0000a000
NIP: 7FF3B564 XER: 00000000 LR: 7FF3B53C REGS: 7faedb40 TRAP: 0200 DAR: 00000000
MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 7FF3B53C 7FAEDC30 7FAEDEF8 00000009 0000003A 00000030 00000020 FFFFFFFE
GPR08: 00000000 00000020 FFD00000 7FAEDC30 7FEFE444 00000000 00000004 00000000
GPR16: 00000004 7FF53478 00000000 0000002E FFFFFF97 7FF435BC 7FF4D1F4 7FF53470
GPR24: 7FF47C6C 00000009 00000008 FFD00000 FFD00000 00000040 7FF57950 00000004
MCSR=0x0000a000 MCSRR0=0x7ff3b564
MCSRR1=0x00029200 MCAR=0x00000000
Call backtrace:
7FF3B53C 7FEFE490 7FF16308 7FF06908 7FF070C8 7FF07178 7FF14C84
7FF04A6C 7FF07A38 7FF34A04 7FF07D70 7FEF1050
Skipping current instr, Returning to 0x7ff3b568
00000030Machine check in kernel mode.
Caused by (from mcsr): mcsr = 0x0000a000
=> reginfo
TLBCAM entries
entry 00: V: 1 EPN 0xfffff000 RPN 0x7ffff000 size:4 KiB
entry 01: V: 1 EPN 0xfe000000 RPN 0xffe000000 size:16 MiB
entry 02: V: 1 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 03: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 04: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 05: V: 1 EPN 0xf4000000 RPN 0xff4000000 size:16 MiB
entry 06: V: 1 EPN 0xf5000000 RPN 0xff5000000 size:16 MiB
entry 07: V: 1 EPN 0xf6000000 RPN 0xff6000000 size:16 MiB
entry 08: V: 1 EPN 0xf7000000 RPN 0xff7000000 size:16 MiB
entry 09: V: 1 EPN 0xf0000000 RPN 0xf00000000 size:4 MiB
entry 10: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 11: V: 1 EPN 0xffd00000 RPN 0xfffd00000 size:256 KiB
entry 12: V: 1 EPN 0x00000000 RPN 0x00000000 size:1 GiB
entry 13: V: 1 EPN 0x40000000 RPN 0x40000000 size:1 GiB
entry 14: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 15: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 16: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 17: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 18: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 19: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 20: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 21: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 22: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 23: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 24: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 25: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 26: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 27: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 28: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 29: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 30: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 31: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 32: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 33: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 34: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 35: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 36: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 37: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 38: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 39: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 40: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 41: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 42: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 43: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 44: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 45: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 46: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 47: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 48: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 49: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 50: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 51: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 52: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 53: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 54: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 55: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 56: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 57: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 58: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 59: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 60: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 61: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 62: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
entry 63: V: 0 EPN 0x30000000 RPN 0x30000000 size:4 KiB
Local Access Window Configuration
LAWBARH00: 0x0000000f LAWBARL00: 0xf4000000 LAWAR00: 0x81800018
(EN: 1 TGT: 0x18 SIZE: 32 MiB)
LAWBARH01: 0x0000000f LAWBARL01: 0xf6000000 LAWAR01: 0x83c00018
(EN: 1 TGT: 0x3c SIZE: 32 MiB)
LAWBARH02: 0x0000000f LAWBARL02: 0xffd00000 LAWAR02: 0x81f00010
(EN: 1 TGT: 0x1f SIZE: 128 KiB)
LAWBARH03: 0x0000000f LAWBARL03: 0x00000000 LAWAR03: 0x81d00015
(EN: 1 TGT: 0x1d SIZE: 4 MiB)
LAWBARH04: 0x00000000 LAWBARL04: 0x00000000 LAWAR04: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH05: 0x00000000 LAWBARL05: 0x00000000 LAWAR05: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH06: 0x00000000 LAWBARL06: 0x00000000 LAWAR06: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH07: 0x00000000 LAWBARL07: 0x00000000 LAWAR07: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH08: 0x00000000 LAWBARL08: 0x00000000 LAWAR08: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH09: 0x00000000 LAWBARL09: 0x00000000 LAWAR09: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH10: 0x00000000 LAWBARL10: 0x00000000 LAWAR10: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH11: 0x00000000 LAWBARL11: 0x00000000 LAWAR11: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH12: 0x00000000 LAWBARL12: 0x00000000 LAWAR12: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH13: 0x00000000 LAWBARL13: 0x00000000 LAWAR13: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH14: 0x00000000 LAWBARL14: 0x00000000 LAWAR14: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH15: 0x00000000 LAWBARL15: 0x00000000 LAWAR15: 0x8100001e
(EN: 1 TGT: 0x10 SIZE: 2 GiB)
IFC Controller Registers
CSPR0:0xFFD00105 AMASK0:0xFFFF0000 CSOR0:0x00020181
IFC_FTIM0:0x10040004
IFC_FTIM1:0x01001800
IFC_FTIM2:0x01100040
IFC_FTIM3:0x00000000
CSPR1:0x00000000 AMASK1:0x00000000 CSOR1:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR2:0x00000000 AMASK2:0x00000000 CSOR2:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR3:0x00000000 AMASK3:0x00000000 CSOR3:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR4:0x00000000 AMASK4:0x00000000 CSOR4:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR5:0x00000000 AMASK5:0x00000000 CSOR5:0x0000000C
IFC_FTIM0:0x00000000
IFC_FTIM1:0x00000000
IFC_FTIM2:0x00000000
IFC_FTIM3:0x00000000
CSPR6:0x00000000 AMASK6:0x00000000 CSOR6:0x0000000C
IFC_FTIM0:0x00000000
解決思路：
CPLD 可以通路了，根本原因我現在使用36bit實體位址，是以下面宏必須要打開
#define CONFIG_SYS_CPLD_BASE 0xffd00000
#ifdef CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#else
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
#endif
#define CONFIG_SYS_CSPR0_EXT (0x0f)
#define CONFIG_SYS_CSPR0 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_16 \
| CSPR_MSEL_GPCM | CSPR_V)
#define CONFIG_SYS_AMASK0 IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR0 0x00020181
#define CONFIG_SYS_CS0_FTIM0 0x10040004
#define CONFIG_SYS_CS0_FTIM1 0x01001800
#define CONFIG_SYS_CS0_FTIM2 0x01100040
#define CONFIG_SYS_CS0_FTIM3 0x00000000
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