;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
;=========================================
//彙編不能使用include包含頭檔案是以用Get，彙編也不認識*.h 檔案,隻能用*.inc，這三條是頭檔案包含的意思
GET option.inc;
GET memcfg.inc
GET 2440addr.inc
BIT_SELFREFRESH EQU (1<<22) //EQU的作用和#define相似
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;The location of stacks
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;Check if tasm.exe(armasm -16 [email protected] 1.0) is used. //16位編譯環境使用tasm.exe編譯
GBLL THUMBCODE //GBLL僞操作聲明一個全局的邏輯變量，并将其初始化成FALSE
//CONFIG ADS定義的内部變量,屬于内置變量，含義為：如果彙編器編譯的為ARM指令，其{CONFIG} 傳回為32，
//如果彙編器編譯的為T指令，其{CONFIG} 傳回為16。 {}代表引用該變量名
[ {CONFIG} = 16 //"["表示"if","|"表示"else","]"表示"endif"
THUMBCODE SETL {TRUE} //SETL指派運算，L表示用于給一個邏輯變量指派
CODE32
//CODE16僞指令通知編譯器，其後的指令序列為16位的Thumb指令。
//CODE32僞指令通知編譯器，其後的指令序列為32位的ARM指令。
//另一方面暫且把處理器設定成為ARM模式，以友善初始化
|
THUMBCODE SETL {FALSE}
]
//MACRO僞操作辨別宏定義的開始，MEND辨別宏定義的結束。用MACRO及MEND定義一段代碼，稱為宏定義//體，這樣在程式中就可以通過宏指令多次調用該代碼段。
MACRO
MOV_PC_LR
[ THUMBCODE
bx lr // bx lr的作用等同于mov pc,lr
| // ARM體系結構中LR的特殊用途有兩種：一是用來儲存子程式傳回位址；二是當異常發生時，LR中//儲存的值等于異常發生時PC的值減4（或者減2），是以在各種異常模式下可以根據LR的值傳回到異常發生前的//相應位置繼續執行。
mov pc,lr
]
MEND
MACRO
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr //相等則跳轉，相等與否由寄存器某些位确定，在此處，由其上一句的指令執行結果決定
|
moveq pc,lr
]
MEND
MACRO
$HandlerLabel HANDLER $HandleLabel
//$HandlerLabel 和 $HandleLabel是兩個參數，第一個參數和第二個參數是不一樣的，中間少了個r，而第一個參數//在本宏中是一個标号，而第二個函數是一個入口位址。
$HandlerLabel
sub sp,sp,#4 ;decrement sp(to store jump address)
stmfd sp!,{r0} ;PUSH the work register to stack(lr does not push because it return to original address)
ldr r0,=$HandleLabel;load the address of HandleXXX to r0
//ldr完成從存儲器中裝載資料到通用寄存器
ldr r0,[r0] ;load the contents(service routine start address) of HandleXXX
str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
//str是寄存器資料到記憶體，即存儲
ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR) //感歎号表示更新寄存器值
MEND
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT MMU_SetAsyncBusMode
IMPORT MMU_SetFastBusMode ;
IMPORT Main ; The main entry of mon program
IMPORT CopyProgramFromNand //引入外部的函數
//AREA 指令訓示彙程式設計式彙編一個新的代碼段或資料段。段是獨立的、指定的、不可見的，它們由連結程式處理。
AREA Init,CODE,READONLY //AREA 段名，屬性，屬性
ENTRY //ENTRY僞操作用于指定彙程式設計式的入口點
EXPORT __ENTRY //EXPORT 僞指令用于在程式中聲明一個全局的标号,該标号可在其他的檔案中引用。
__ENTRY
ResetEntry
//ResetEntry的值在ARM上電運作時是0X00000000，在JTAG仿真時是0X30000000。這個值在拷貝程式時會用到。
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
ASSERT :DEF:ENDIAN_CHANGE // ASSERT 是斷言僞指令,文法是:ASSERT +邏輯表達式
// def 是邏輯僞操作符，格式為： :DEF:label，作用是：判斷label是否定義過
[ ENDIAN_CHANGE
ASSERT :DEF:ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32
b ChangeBigEndian ;DCD 0xea000007 // ChangeBigEndian标号在下文，這句作用為32位長度時跳轉到ChangeBigEndian處
]
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 //16位跳轉到ChangeBigEndian處，長度不同則指令不同
]
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea //8位跳轉到ChangeBigEndian處，長度不同則指令不同
]
|
b ResetHandler //當沒有定義總線寬度時跳轉到複位中斷處,這條語句放在0x00處
]
//啟動代碼開始是一個異常向量表，這個向量表是固定的，由處理器決定，必須要放在0x0位址那個地方，這個跟51單片機的中斷向量表相類似。
//Q:既然ResetEntry的位址是0x0，那麼為什麼上面的指令隻占了4個位元組？
//A:因為上面的指令，ASSERT以及[等都是僞指令，不會編譯為代碼
b HandlerUndef ;handler for Undefined mode //0x04
b HandlerSWI ;handler for SWI interrupt //0x08
b HandlerPabort ;handler for PAbort //0x0C
b HandlerDabort ;handler for DAbort //0x10
b . ;reserved //0x14
b HandlerIRQ ;handler for IRQ interrupt //0x18
b HandlerFIQ ;handler for FIQ interrupt //0x1C
;@0x20
b EnterPWDN ; Must be @0x20.
ChangeBigEndian //标号
;@0x24
[ ENTRY_BUS_WIDTH=32 //DCD指令用于配置設定一片連續的字存儲單元并用指定的資料初始化。
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff //填充作用
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
HandlerFIQ HANDLER HandleFIQ //通過宏的名稱HANDLER調用宏，其中宏的标号為HandlerFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
IsrIRQ
sub sp,sp,#4 //reserved for PC，給PC寄存器保留的值
stmfd sp!,{r8-r9} //把r8-r9壓入棧
ldr r9,=INTOFFSET // ldr完成從存儲器中裝載資料到通用寄存器
ldr r9,[r9]
ldr r8,=HandleEINT0 //這就是我們第二個中斷向量表的入口的,先裝入r8
add r8,r8,r9,lsl #2 //lsl #2表示r9左移兩位
ldr r8,[r8]
str r8,[sp,#8] //str是寄存器資料到記憶體，即存儲
ldmfd sp!,{r8-r9,pc} //出棧操作，感歎号表示更新寄存器值
// LTORG用于聲明一個資料緩沖池，（也稱為文字池）的開始。在使用僞指令LDR時，常常需要在适當的地方加入LTORG聲明資料緩沖池，LDR加載的資料暫時被編譯器放于資料緩沖池中。LTORG僞操作通常放在無條件跳轉指令之後，或者子程式傳回指令之後，這樣處理器就不會錯誤的将資料緩沖池中的資料當作指令來執行。
LTORG
;=======
; ENTRY
;=======
ResetHandler
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0xffffffff ;all interrupt disable
str r1,[r0]
ldr r0,=INTSUBMSK
ldr r1,=0x7fff ;all sub interrupt disable
str r1,[r0]
[ {TRUE}
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPBCON
ldr r1,=0x00555555
str r1,[r0]
ldr r0,=GPBDAT
ldr r1,=0x07fe
str r1,[r0]
]
;To reduce PLL lock time, adjust the LOCKTIME register.
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]
[ PLL_ON_START
; Added for confirm clock divide. for 2440.
; Setting value Fclk:Hclk:Pclk
ldr r0,=CLKDIVN
ldr r1,=CLKDIV_VAL ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
str r1,[r0]
; MMU_SetAsyncBusMode and MMU_SetFastBusMode over 4K, so do not call here
; call it after copy
; [ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
// MMU_SetAsyncBusMode 和 MMU_SetFastBusMode 都在4K代碼以上, 如果你想你編譯出來的程式能在NAND上運作的話,就不要在這調用這兩函數了不能用這兩函數,自己寫還不行嗎,下面的代碼這這麼來了,實作和上面兩函數一樣的功能
;program has not been copied, so use these directly
[ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
;Configure UPLL
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
str r1,[r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for
setting hardware be completed.
nop
nop
nop
nop
nop
nop
;Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;Fin=16.9344MHz
str r1,[r0]
]
;Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP //檢視是否是由睡眠狀态啟動，如果是則跳轉到WAKEUP_SLEEP狀态
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA ;be careful!
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
; check if EIN0 button is pressed //如果 EINT0 産生(這中斷就是我們按鍵産生的), 就清除SDRAM
ldr r0,=GPFCON
ldr r1,=0x0
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 //如果沒有按,就跳到後面的1标号處 => Initialize stacks
; Clear SDRAM Start //如果按下鍵則進行清除SDRAM的操作
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0 //0表示局部标号，可以重複出現
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0 //%B 代表，往前搜尋 lable為0的行；bne %F1，這是向後搜尋lable為１的行
;Clear SDRAM End
1
;Initialize stacks
bl InitStacks
;===========================================================
// BL指令在轉移到子程式執行之前，将其下一條指令的位址拷貝到R14（LR,連結寄存器）。由于BL指令儲存了下條指令的位址，是以使用指令“MOV PC ,LR”即可實作子程式的傳回。
ldr r0, =BWSCON
ldr r0, [r0] //BWSCON的[2:1]反映了外部引腳OM[1:0]:若OM[1:0] != 00, 從NOR FLash啟動或直接在記憶體運作；若OM[1:0]==00，則為Nand Flash Mode
ands r0, r0, #6 //#6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg //OM[1:0] != 00，NOR FLash boot，不讀取NAND FLASH
adr r0, ResetEntry ;OM[1:0] == 0, NAND FLash boot
cmp r0, #0 ;if use Multi-ice, //如果R0等于0，那麼它就将狀态寄存器中的Z置為1
//如果是0才是真正從NAND 啟動，因為其4k被複制到0位址開始的stepingstone 内部sram中, 如果!=0,說明在using ice, 這種情況也不讀取NAND FLASH, JTAG調試時是直接下載下傳到SDRAM中運作，不需要再從nand拷貝
bne copy_proc_beg ;do not read nand flash for boot //不為0就跳轉
;nop
;===========================================================
nand_boot_beg //這一段代碼完成從NAND Flash讀代碼到RAM
[ {TRUE} //個人感覺是宏名使用值的時候加{},變量的話就不用了。。。
bl CopyProgramFromNand // CopyProgramFromNand是一個外部的函數
|
mov r5, #NFCONF //首先設定NAND的一些控制寄存器
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID //按着讀取NAND的ID号,結果儲存在r5裡
mov r6, #0
ldr r0, =0xec73 //期望的NAND ID号
cmp r5, r0
beq %F1
ldr r0, =0xec75 //期望的另一個NAND ID号
cmp r5, r0
beq %F1 //相等的話就跳到下一個1标号處
mov r6, #1 //不相等,設定r6=1
1
bl ReadNandStatus //讀取NAND狀态,結果放在r1裡
mov r8, #0 //r8設初值0,意義為頁号
ldr r9, =ResetEntry //這裡使用的是ldr僞指令,而不是上面用的adr僞指令,它加載的是ResetEntry的絕對位址,也就是我們期望的RAM中的位址,在這裡,它和|Image$$RO$$Base|一樣
2
ands r0, r8, #0x1f //凡r8為0x1f(32)的整數倍-1,eq有效,ne無效
bne %F3
mov r0, r8
bl CheckBadBlk
cmp r0, #0
addne r8, r8, #32 //存在壞塊的話就跳過這個壞塊: + 32得到下一塊. 故: r8 = blockpage addr，因為讀寫是按頁進行的(每頁512Byte)
bne %F4
3
mov r0, r8
mov r1, r9
bl ReadNandPage
add r9, r9, #512 //每一頁的大小是512Bytes
add r8, r8, #1
4
cmp r8, #5120 //比較是否讀完5120頁即2.5M Bytes
bcc %B2
mov r5, #NFCONF ;DsNandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
]
ldr pc, =copy_proc_beg
;===========================================================
copy_proc_beg
adr r0, ResetEntry
ldr r2, BaseOfROM
cmp r0, r2 //比較 ResetEntry 和 BaseOfROM
ldreq r0, TopOfROM //如果相等的話(在記憶體運作 --- ice -- 無需複制code區中的ro段，但需要複制code區中的rw段),TopOfROM->r0
beq InitRam
//下面這個是針對代碼在NOR FLASH時的拷貝方法功能為把從ResetEntry起,TopOfROM-BaseOfROM大小的資料拷到BaseOfROM //TopOfROM和BaseOfROM為|Image$$RO$$Limit|和|Image$$RO$$Base||Image$$RO$$Limit|和|Image$$RO$$Base|由連接配接器生成為生成
//的代碼的代碼段運作時的起啟和終止位址BaseOfBSS和BaseOfZero為|Image$$RW$$Base|和|Image$$ZI$$Base| |Image$$RW$$Base|和//|Image$$ZI$$Base|也是由連接配接器生成兩者之間就是初始化資料的存放地
ldr r3, TopOfROM
ldmia r0!, {r4-r7} //開始時，r0 = ResetEntry --- source
stmia r2!, {r4-r7} //開始時，r2 = BaseOfROM --- destination
cmp r2, r3 //終止條件：複制了TopOfROM-BaseOfROM大小
bcc %B0
sub r2, r2, r3
sub r0, r0, r2
InitRam
ldr r2, BaseOfBSS
ldr r3, BaseOfZero
cmp r2, r3
ldrcc r1, [r0], #4
strcc r1, [r2], #4
bcc %B0
mov r0, #0
ldr r3, EndOfBSS
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
ldr pc, =%F2 ;goto compiler address
2
; [ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there is not 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
; ;Copy and paste RW data/zero initialized data
; ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
; ldr r1, =|Image$$RW$$Base| ; and RAM copy
; ldr r3, =|Image$$ZI$$Base|
;
; ;Zero init base => top of initialised data
; cmp r0, r1 ; Check that they are different
; beq %F2
;1
; cmp r1, r3 ; Copy init data
; ldrcc r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
; strcc r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
; bcc %B1
;2
; ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
; mov r2, #0
;3
; cmp r3, r1 ; Zero init
; strcc r2, [r3], #4
; bcc %B3
[ :LNOT:THUMBCODE // L是logic邏輯 NOT就是not判斷THUMBCODE的邏輯真假
bl Main ;Do not use main() because ......
;ldr pc, =Main ;
b .
]
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Do not use main() because ......
b .
CODE32
]
;function initializing stacks
InitStacks
;Do not use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
mov pc,lr
;The LR register will not be valid if the current mode is not SVC mode.
;===========================================================
[ {TRUE}
|
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr //調用傳回
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
]
;===========================================================
LTORG
;GCS0->SST39VF1601
;GCS1->16c550
;GCS2->IDE
;GCS3->CS8900
;GCS4->DM9000
;GCS5->CF Card
;GCS6->SDRAM
;GCS7->unused
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+
(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+
(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+
(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+
(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+
(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+
(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+
(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)
DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON
tst r0,#0x8 ;SLEEP mode?
bne ENTER_SLEEP
ENTER_STOP
ldr r0,=REFRESH
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0 subs r1,r1,#1
bne %B0
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0 subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
; Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be
needed.
0 subs r1,r1,#1
bne %B0
ldr r1,=MISCCR
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;Set memory control registers
ldr r0,=SMRDATA ;be careful!
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
mov r1,#256
0 subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Do not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END
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