1、
警告如下：
Warning (10240): Verilog HDL Always Construct warning at spi_wr.v(108): inferring latch(es) for variable "csn", which holds its previous value in one or more paths through the always construct…… 原先的警告說明，你沒有在所有狀态指派，在這些狀态将保持
參考網頁：http://zhidao.baidu.com/link?url=BoZc_q3DigdvwHJUbs6KyCoFVahLNc49LwHbkb4G91HlOYaAr3UY2mpKyV4ubY8V0WyUtqHDbL_vXl0qC9hC8_
![關于latch: cache buffers chains的sql優化[圖]](data:image/gif;base64,R0lGODlhAQABAIAAAP///wAAACwAAAAAAQABAAACAkQBADs=)