RISC-V開發工具 | 使用CDS進行RISC-V硬體平台的開發和調試

本文作者：蔣龍

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使用CDS進行RISCV硬體平台的開發和調試

全文中英文

Hello everyone, my name is Peter, and I come from Alibaba Group. Today I am very happy to introduce a new development tool for CORE-V platform. CDS, the full name is Chip Development Suite.

大家好，我是來自阿裡巴巴的Peter。今天我非常高興給大家介紹一款CORE-V平台的開發工具，CDS，全程是Chip Development Suite

CDS is an eclipse-based graphical development tool, and we use eclipse plus more than 40 plug-ins to makes it into CDS. With CDS, a developer can create a new project based on CORE-V core, then coding and building the project. CDS also provides the flash loader and debugger which can help developers download images into target and debug the target in a graphical debugger view.

CDS是一款基于eclipse的圖形開發工具，我們在eclipse基礎上增加了超過40個插件，進而變成了CDS，使用CDS，開發者可以建立基于CORE-V核的工程，并且能夠進行代碼開發和編譯。CDS也提供了Flash下載下傳器、調試器等，這些工具可以幫助開發者将程式鏡像下載下傳到嵌入式裝置端，并進行圖形化的調試。

So, today I will give you a show about how to create and debug a CORE-V project in CDS. Before the presentation, we should do some preparation:

今天我将給大家示範，如何在CDS中建立和調試一個CORE-V的工程。在示範之前，我們需要做一些準備工作。

We will use GENESYS2 FPGA board to simulate a CORE-V platform, I have prepared the bit files which uses the default USB cable for debugging, and I got the SDK from github: the pulp-runtime project and the pulp-runtime-examples project. In CDS, we use some examples from the pulp-runtime-examples project, and put the source files together with pulp-runtime project, and make these files into CDS projects. Besides, I have configured the board with “USB/SD” config mode to start GENESYS2 board.

我們使用GENESYS2 FPGA開發闆來模拟CORE-V硬體平台，工程使用github上開源的pulp-runtime工程。在CDS中，我們使用了一些從github上下載下傳的開源例程。我已經配置了GENESYS2開發闆為USB/SD的工作模式。

Before starting CDS, we should connect the GENESYS2 board at first. Just prepare one USB line, and connect it from computer’s USB port to the USB cable for debugging on GNENSYS2 board.

啟動CDS之前，我們需要準備一個USB線，一端連接配接電腦，一段連接配接GENESYS2開發闆上的USB調試口。

After this preparation, we can start CDS in PC, just double click the icon in the desktop, and then choose a folder as the workspace in CDS.

上手準備完成以後，我們可以啟動CDS，隻需要輕按兩下雙面CDS圖示，然後選擇一個目錄作為CDS工作空間。

when enter the workspace at the first time, CDS will show the welcome page, we can create the project by clicking “project creator”, and also, we can create a project in project explorer view. Right click blank area in project explorer, chose T-Head CPU project, and in the popup dialog, we can see all the project templates which supported by CDS. Here we have added CORE-V project templates into CDS, a user can find CORE-V platform in “Target Template Selected” tree view. Now there are two project templates here, we chose the simple as the template to create a new CORE-V project, just input project name, and click finish.

首次進入工作空間，CDS将會顯示welcome頁面，我們可以點選project creator圖示進行工程建立，也可以在工程視窗中建立工程。右擊工程視窗空白位置，選擇T-HEAD CPU工程，然後彈出對話框，我們可以看到CDS支援的全部工程模闆。這裡我們已經将CORE-V工程模闆加入CDS中，使用者可以在Target Template Select視圖中找到CORE-V平台。現在這裡有兩個CORE-V工程，我們選擇一個簡單的工程模闆用來建立一個全新的CORE-V工程，在這裡輸入工程名，點選Finish

After finish creating project, we can right click project node, and start to build our project.

完成工程建立，我們右擊工程節點，選擇build工程

Now project is built successfully, next, we can start to debug it on the GENESYS2 board. Just right click the project and chose “Debug As-> T-Head Application”. Then CDS goes into the debug perspective, connects the board and automatically downloads the images into the GENESYS2 board and then auto run the program into main, just like this.

現在工程成功編譯，我們可以在GENESYS2開發闆上進行調試。直接右擊工程，選擇Debug As->T-Head Application，然後CDS進入了調試視圖，連接配接開發闆，并自動将程式下載下傳到GENESYS2開發闆中，最後運作程式到main函數，就像目前這樣。

When success to go to main function, CDS has been in debug perspective, in this perspective, we can control the board’s state, we can run the board by click continue button, we can also let the board execute the project by stepping the source code, just like this.

但我們進入main函數以後，CDS已經在調試視圖中了，在這裡視圖夏，我們可以控制開發闆的狀态，我們可以通過點選continue按鈕運作開發闆，我們可以點選單步按鈕，單步執行我們的工程，就像這樣。

In “Disassembly View”, we can see the current position of the program, and see the next instructions which will be executed by CORE-V CPU.

在反彙編視窗中，我們可以看到目前程式的位置，并且可以看到後續CORE-V CPU即将執行的指令。

And in “Debug View”, we can see the call stacks of the program, and find the source code by click each frame, besides, the disassembly view also changes the display according to the selected frame

在Debug視圖中，我們可以看到程式的調用棧，并且通過點選每個幀，可以看到對應幀的源代碼，此時反彙編視窗也會顯示對應的指令。

We can read and write the CORE-V’s registers in the “Register View”, To access the variables of the program, we should use “Variable view”. In the “Expression View”, we can input any variable or symbol of our project, and read it or modify it.

我們可以在寄存器視窗中讀寫CORE-V的寄存器。變量視窗中可以通路程式的變量。在表達式視窗中，我們可以輸入工程中的任何符号，并且可以讀寫符号對應的記憶體值。

So, that is the first part of my presentation about how to develop and debug a CORE-V platform with CDS.

以上是我們的第一部分示範，示範了如何在CDS中開發和調試一個CORE-V平台

For the above demo, I must say thanks to Hugh, because he helps me a lot about how to start the GENESYS2 board, and with his help, I can integrate CORE-V project into CDS in a short time.

關于上述demo，我非常感謝Hugh（CORE-V的一個人員），因為他給了我很多的幫助，讓我們能夠啟動GENSYS2開發闆，并且在他的幫助夏，我很快地将CORE-V工程內建到了CDS中。

Now, I want to show another powerful feature of our CDS, it’s called “T-Head Profiling”

現在，我将給你們展示CDS的另外一個重要功能，T-Head Profiling

As we have known, CDS is an IoT IDE for CORE-V cores, in CDS, a user can create, build and debug a CORE-V based project, besides, CDS provides many other functions which will help developer create a high performance and low power images as soon as possible, the “T-Head Profiling” is one of those functions.

正如我們所知道的，CDS是一個開發調試CORE-V的IoT內建開發環境，使用者可以在CDS中建立、調試CORE-V工程，此外，CDS還提供了其他可以幫助開發者開發出高性能、低功耗鏡像的功能，T-Head Profiling就是其中一個。

In CDS, we can start the T-Head profiling for some project in an easy way, now I will show it.

在CDS中，我們可以很友善地為一些工程啟動T-Head Profiling功能，現在我将示範一下。

Here is the same project that I just created, we can see the main logic, this is some simple arithmetic operations.

這裡是我剛剛建立的工程，我們可以看到main函數的邏輯，這裡有一些簡單的算術操作。

If these operations are part of a real logic for some algorithm, there will be a very practical question: what is the hotspot code block of this algorithm? and which function should I put more energy to optimize? The answer is using CDS “T-Head Profiling”

加入這裡的操作邏輯是一個真實的算法中的一部分，那麼将會有個工程性的問題：這個算法的熱點代碼是什麼?我應該在哪個函數上花較多的精力去優化？使用CDS的T-Head Profiling功能将很好地解決這些問題。

Right now, the “t-head profiling” only support project which will run in the simulator instead of real hardware, so here we have configured a simulated platform for this CORE-V project, let me show it, just right click project and select profile configuration, double click t-head profiling, then we success to create a profiling configuration for our project, we can see the project has the default platform, xxxxxxx

目前，T-Head Profiling功能僅支援模拟器運作，是以這裡我們配置了一個CORE-V工程的模拟平台。右擊工程，選擇Profile Configuration，輕按兩下T-Head Profiling，然後我們成功的建立了一個profiling配置，我們可以看到種類預設的虛拟平台。

We can click profile to start t-head profiling, CDS will show the “Profiling Running” page… in this page, we could see the dynamic situation of the program’s execution which includes hotspot function rank, the memory access, interrupt and fast interrupt info.

我們可以點選Profile來啟動T-Head Profiling功能，CDS将會顯示Profiling Running頁面，在這個頁面中給，我們可以看到程式的動态運作狀态，包括熱點函數排序、記憶體通路、中斷資訊。

After click “Finish Profiling” button, “Profiling Overview” page pops up, this page shows the cycles rank of five top functions, Here shows the instructions total number of each instruction type. It also shows the I/D cache miss rate & branch predict rate, for those CPUs which have such hardware modules.

點選Finish Profiling按鈕以後，會彈出Profiling Overview頁面，在這個頁面中，會展示周期前五的函數，這裡會展每個指令類型的總數，還有為哪些包含相關硬體的CPU展示cache miss率和分支預測準确率。

The “TimeLine” page gives the whole execution lifetime of the program, we can see the instruction stream of any range of the lifetime. When we double click any time point in timeline, the executed instructions during this time range will show here, by double clicking each line of the list, we will locate the corresponding source code. We can also narrow the time line, and see the detail executed instructions info.

TimeLine頁面展示了程式運作的全部運作時間，我們可以看到整個程式運作的指令流，我們可以輕按兩下任何時間點，此時刻的指令流會顯示在這裡，輕按兩下每個指令，可以看到該指令對應的源代碼。我們可以通過縮短時間線，來看到程式執行流的細節資訊。

In the “Function” page, we can see all functions list, the instruction column shows the total instructions in this function except its sub functions, the cycle column shows total cycles in the function except its sub functions. we can click each column header to rank the list according to the column header.

在Function頁面中，我們可以看到全部函數清單，insn列顯示了目前函數執行的指令總數，cycle列顯示了目前函數執行的周期數。通過點選每個列，可以按照該列對目前函數進行排序。

The last but not the least, the “Call Paths” view. This view shows the dynamic call paths of the program, this page’s columns are similar with “Function” page, but the page shows a tree view instead of a list. In Call Paths tree, we can see the dynamical execution call path, and we can find each function’s instructions and cycles info in that path.

最後，Call Paths視圖顯示了程式動态調用軌迹。該頁面的列類似于Function視圖，但是種類使用了樹形展示，在Call Paths樹中，我們可以看到程式動态調用路徑，我們可以找到每個函數的指令和周期資訊。

And that’s all for the T-Head Profiling, I hope this function can help users optimize the program which run in CORE-V platform

以上就是T-Head Profiling的全部功能，希望這個功能可以幫助開發人員優化運作在CORE-V平台上的程式。

Thanks for your attention.

感謝。